Difference between reg, wire, logic in SystemVerilog


Can be used for input, output, inout

Multiple drivers, No drivers cause x


Wire variable = value;

Assign variable = value;

Can be used to connect module instances



Can be used only for input

Can’t be used in ‘assign’ statement

It takes last assigned value, behaves like a variable


R <= 1;

R <= 0;

R takes value 0, even though there are multiple concurrent assignments



Can be used for input, output. Can’t be used for inout

Can be used in place of wire or reg;

First usage defines the behavior; can’t be changed later.


Assign l = 1; // Valid

Initial l = 1; // Valid

Assign l = 0; initial l = 1; // Invalid



Similar to logic; it is a two state variable.


Non-blocking assignment

No assignment happens to lhs till simulation timestamp is advanced.

Even after #0, the assigned value will not available


Blocking assignment

Lhs gets assigned immediately


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