Open Drain Lines


EBD file simulation

Data Acquisition

Logic Families Voltage Translation

No Translation required for the following:

[TTL] to [TTL]

[TTL] to [CMOS with input switching at TTL levels]

[CMOS 5V] to [TTL]



Translation required for the following:

[TTL] to [CMOS*]

            Pull up of 1k to 2k required

            TTL outputs 2.4V to 3.3V for a high level

            CMOS required 3.7 for high level.

            The pull up resister increases the output voltage (of TTL driver).


[CMOS*] to [TTL]


*The translation depends on the VCC of CMOS device.



[TTL] to [ECL]  /   [ECL] to [TTL]

            TTL to ECL (ECL to TTL) translator along with ECL termination resistors are needed.


[PECL] to [TTL]  /  [TTL] to [PECL]

            PECL is Positive ECL

            PECL to TTL (TTL to PECL) translator needed.

[PECL] to [CMOS]  /  [CMOS] to [PECL]

            Same as above, but pull of 1k to 2k is required for CMOS.



[PECL 5V] to [LVDS 5V]

            Pull up both +,- signals to 3V through 50E resistors.


[LVPECL 3.3V] to [LVDS 5V]

            Pull up both +,- signals to 1.3V through 50E resistors




Signal Integrity Principles

Each interconnect is a transmission line

Forget the word ground; Think return path.

Bandwidth of a signal is the highest sine wave frequency component.

All SI formulas are definitions or approximations.


Even a two inch long trace on a PCB can affect SI.


SI problems: Timing, Noise, EMI

Noise sources:

Signal on a net: Reflections, Distortions from Impedance discontinuities

Crosstalk: Mutual Inductance, Mutual (parasitic) capacitance

Rail collapse: Voltage drop in power/ground.

EMI: A component or entire system


Impedance discontinuities: Cross section, topology, added components(via, connector, etc.)


Ways to minimize cross talk (cross talk should kept as minimum as 5%)

1) Use uniform plane as return path.

2) Spacing traces farther apart.

3) Use guard traces.


Rail-Collapse noise (Rail-bounce, Ground bounce):

Because of the impedance of the power and ground distribution, a voltage drop will occur as the IC current switches. This voltage drop means the power and ground rails have collapsed from their nominal values.

Simultaneous switching noise (SSN) or simultaneous switching output (SSO): Whenever an output pin changes state, the current it draws from its ICs 0V and power rails eventually flows through the interconnections to the PCB’s 0V and power rails. The inductance in these paths causes voltage drops that make the IC’s internal 0V and power rails ‘bounce’ with respect to the PCB rails, according to the activity of the output ports

Ways to minimize:

1) Closely placed power-ground planes with thin dielectric

2) Low inductance decaps, on-chip decaps

3) Multiple short power, ground pins in packages


Sources of EMI

1) Conversion of some differential signal into a common signal

2) Ground bounce

Ways to minimize:

1) Use shielded cables

2) Use low-impedance connections


Rise time: Time taken to go from 10% to 90% of the final value.

Mostly rise time is about 10% of clock period.


Bandwidth = 0.35*[Rise Time]

For most microprocessor, ASIC based systems rise time is 7% of clock period.

Approximately bandwidth is five times the clock frequency.


An electron travels (in a copper wire) at a speed of 1cm/s.

Time to travel down a 6” of interconnect in FR4 is about 1ns.