Friis transmission equation

Path loss = 20 log (4 * pi * r / lambda)

[Note: use log base 10]


Path loss = signal attenuation. Unit: dB

pi = 22 / 7

r = distance between transmitter and receiver. Unit: m

lambda = wavelength of signal. Unit: m

Wavelength = C/f


C = speed of electromagnetic waves in free space

= 299792458. Unit: m / s

f = frequency of signal. Unit: Hz

Let r = R * (2 ^ x)

Path loss = 20 log (4 * pi * R * L / lambda)

= 20 log (4 * pi * R / lambda) + 20 log (2 ^ x)

= 20 log (4 * pi * R / lambda) + 6x

The above derivation implies range(R) doubles every 6dB of path loss.

The path loss is +8.519dB more over a given range for the 2.4 GHz compared to 900MHz for the same range. In other words operating at 900 MHz exhibits a significantly longer range than is possible at 2.4 GHz.


links for 2007-03-14

EBD file simulation

ADC Selection

DC coupling vs AC coupling

DC coupling allows both AC and DC signals through, while AC coupling accepts only AC signals.


Issue in AC coupling:  AC coupling rejects DC component in the signal, making

the average value of the signal to zero. 

Case 1: Waveform has 50% duty cycle, the peak value in both positive and negative cycles will be same. 

Case 2: Waveform doesn’t have 50% duty cycle.

After AC coupling, (average value is zero)

Area under the positive half cycle = Area under negative half cycle.

But the peak value for positive and negative half cycles will not be same.


Example:  Consider a square wave with duty cycle 1/3 and peak-to-peak value 3V.

After AC coupling, the peak values would become 2V, -1V respectively.

If the AC coupled device detects 1.5V as logic high,

-1.5V as logic low,  due to the above effect, there would be erroneous detection.

Logic Families Voltage Translation

No Translation required for the following:

[TTL] to [TTL]

[TTL] to [CMOS with input switching at TTL levels]

[CMOS 5V] to [TTL]



Translation required for the following:

[TTL] to [CMOS*]

            Pull up of 1k to 2k required

            TTL outputs 2.4V to 3.3V for a high level

            CMOS required 3.7 for high level.

            The pull up resister increases the output voltage (of TTL driver).


[CMOS*] to [TTL]


*The translation depends on the VCC of CMOS device.



[TTL] to [ECL]  /   [ECL] to [TTL]

            TTL to ECL (ECL to TTL) translator along with ECL termination resistors are needed.


[PECL] to [TTL]  /  [TTL] to [PECL]

            PECL is Positive ECL

            PECL to TTL (TTL to PECL) translator needed.

[PECL] to [CMOS]  /  [CMOS] to [PECL]

            Same as above, but pull of 1k to 2k is required for CMOS.



[PECL 5V] to [LVDS 5V]

            Pull up both +,- signals to 3V through 50E resistors.


[LVPECL 3.3V] to [LVDS 5V]

            Pull up both +,- signals to 1.3V through 50E resistors