Compilation error at UVM factory registration macros

package simple_pkg;

import uvm_pkg::*;

`include “uvm_macros.svh”

class my_class extends uvm_object;


function new(string name=””,int additional_arg);;




The above package seems to be syntactically correct. But compiler(Eg. Cadence irun) throws error.

Compilation error: `uvm_object_utils(my_class). Task/function call, or property/sequence instance does not specify all required formal arguments.

`uvm_object_utils macro tries to register with factory, where the function new doesn’t have additional args.

Compiler throws error due to ‘additional_arg’ to function new. Remove this and compilation error goes off.

Error message is not clear and seems irrelevant to the issue here – a disadvantage of using macros; the macro expands into something that we can’t visualize.


Summary: Avoid additional args to ‘new’ function when using UVM factory registration.



SystemVerilog Array of Interfaces

// Viewing Array of interfaces in waveform viewer(dve)

// Notes added inline in the below example

interface my_if(input clk);
logic [31:0] addr;
logic [31:0] data;

module dut(input xx, my_if i[1:0], output o, my_if ii);
assign o = xx ? i[0].data :;

module tb;

bit o;
bit clk;

// Array of interface
// Visible where the actual instance is present
// interface signals can’t be seen as arguments of dut
// Visible under ‘tb’, NOT under ‘dut’
my_if i[1:0](clk);

// interface instance – not an array
// Visible under ‘tb’, as well as under ‘dut’
my_if ii(clk);

dut dut(.xx(1’b1), .i (i[1:0]) , .o, .ii);

initial forever #5 clk++;

initial begin
i[0].addr = 10;
i[0].data = ‘hff;
i[1].addr = 20;
i[1].data = ‘haa; = 0;
i[0].addr = 110;
i[0].data = ‘h1ff;
i[1].addr = 120;
i[1].data = ‘h1aa; = 1;
#100 $finish;

// Waveform dumping for VCS
// Change this for other simulators
initial begin


// Screenshot on waveform viewer (dve)


Difference between reg, wire, logic in SystemVerilog


Can be used for input, output, inout

Multiple drivers, No drivers cause x


Wire variable = value;

Assign variable = value;

Can be used to connect module instances



Can be used only for input

Can’t be used in ‘assign’ statement

It takes last assigned value, behaves like a variable


R <= 1;

R <= 0;

R takes value 0, even though there are multiple concurrent assignments



Can be used for input, output. Can’t be used for inout

Can be used in place of wire or reg;

First usage defines the behavior; can’t be changed later.


Assign l = 1; // Valid

Initial l = 1; // Valid

Assign l = 0; initial l = 1; // Invalid



Similar to logic; it is a two state variable.


Non-blocking assignment

No assignment happens to lhs till simulation timestamp is advanced.

Even after #0, the assigned value will not available


Blocking assignment

Lhs gets assigned immediately

SystemVerilog Interview Questions

What is the use of OOPs in Verification? Compare Verilog and SV.
OOPs allows plug-and-play re-usable verification components
Verilog – Procedural
SystemVerilog – OOPs. Abstraction, Encapsulation, Inheritance, Polymorphism

Packed Array vs Unpacked Array
Packed array – made of sub-dividing a vector into subfields which can be conveniently accessed as array elements. Also is guaranteed to be represented as a contiguous set of bits. Unpacked array may or many not be so represented.

Usage of arrays
Packed/Unpacked array – Size Known at Compile time
Dynamic array – Size Known at Run-time
Queues – Size Varying at Run-time
Associative array – Index/Key can be random. Sparse Memory Models. Scoreboard for out-of-order transactions

Struct vs. Union
Struct occupies memory of Sum of sizes of all members.
Union occupies memory of Largest sized member. All members point to the same memory location. Tagged Union can declare methods of void type.

Struct vs. Class
Struct can’t have methods. No OOPs ??

Reg vs. Logic
Use logic instead of reg. Intent – deprecate use of reg in future.

Protected vs. Private/Local
Private – Members(fields/methods) can only be accessed within the same scope
Protected – Similar to Private except that Members can be accessed in a derived class

What is polymorphism?
Non-OOP form – Function overloading in C++
OOP form – Dynamic lookup of virtual functions

What is virtual function?
Function which can be over-ridden by extending the class

Use of Packages
Explicit named scope. Similar to namespace in C++
It may contain typedef, variables, functions, sequences and properties

Use of Program Block
Eliminate test-bench race by avoiding non-determinism.
Statements (initial blocks) sensitive to design (module) signals are scheduled in Reactive region.
Initial blocks in modules are scheduled in Active region. Design signals driven from program using non-blocking assignments are updated in NBA region.

Use of Virtual Interface
Separate abstract models from actual signals

Latch vs Flip Flop


• Asynchronous

• Level Sensitive

• Clock signal = Enable signal* = Latch Signal

o It is not apt to call it Clock; better call it Enable

o When ‘1’, Q changes when D changes

o When ‘0’, Q retains state

• Used as Mechanical Switch De-bouncer

• Processor ALE signal implemented using Latch

Flip Flop

• Edge Sensitive (Master-Slave Flip Flop)

• Clock signal = Enable signal* = Gating Signal

o When ‘1’, Q depends on D; Q doesn’t change till next Clock.

o When ‘0’, Q retains state

• All sequential logic implemented using Flip Flops