SystemVerilog Array of Interfaces

// Viewing Array of interfaces in waveform viewer(dve)

// Notes added inline in the below example

interface my_if(input clk);
logic [31:0] addr;
logic [31:0] data;
endinterface

module dut(input xx, my_if i[1:0], output o, my_if ii);
assign o = xx ? i[0].data : ii.data;
endmodule

module tb;

bit o;
bit clk;

// Array of interface
// Visible where the actual instance is present
// interface signals can’t be seen as arguments of dut
// Visible under ‘tb’, NOT under ‘dut’
my_if i[1:0](clk);

// interface instance – not an array
// Visible under ‘tb’, as well as under ‘dut’
my_if ii(clk);

dut dut(.xx(1’b1), .i (i[1:0]) , .o, .ii);

initial forever #5 clk++;

initial begin
#10
i[0].addr = 10;
i[0].data = ‘hff;
i[1].addr = 20;
i[1].data = ‘haa;
ii.data = 0;
#10
i[0].addr = 110;
i[0].data = ‘h1ff;
i[1].addr = 120;
i[1].data = ‘h1aa;
ii.data = 1;
#100 $finish;
end

// Waveform dumping for VCS
// Change this for other simulators
initial begin
$vcdplusfile(“waves.vpd”);
$vcdpluson;
$vcdplusmemon;
end

endmodule

// Screenshot on waveform viewer (dve)

Interface_Array

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System Verilog Virtual Interface

Download here. system_verilog_virtual_interface

// Filename    : virtual_interface.sv
// Author      : A.G.Raja
// License     : GPL
// Website     : https://agraja.wordpress.com

interface bus(input wire clk);
int address;
int data;

modport virtual_interface(input clk);
endinterface

module virtual_interface;
bit clk;
bus BUS(clk);
class monitor;
virtual bus VBUS;
task disp;
$display(VBUS.address);
$display(VBUS.data);
endtask
endclass
monitor m;

initial begin
m = new;
m.VBUS = BUS;
BUS.address = 100;
BUS.data    = 1234;
m.disp;
end
endmodule

// Running simulation in ncverilog
// ncverilog +sv virtual_interface.sv

// Running simulation in modelsim/questasim
// vlib work
// vlog -sv virtual_interface.sv
// vsim -c virtual_interface
// run

Download here. system_verilog_virtual_interface