System Verilog Virtual Interface

Download here. system_verilog_virtual_interface

// Filename    : virtual_interface.sv
// Author      : A.G.Raja
// License     : GPL
// Website     : https://agraja.wordpress.com

interface bus(input wire clk);
int address;
int data;

modport virtual_interface(input clk);
endinterface

module virtual_interface;
bit clk;
bus BUS(clk);
class monitor;
virtual bus VBUS;
task disp;
$display(VBUS.address);
$display(VBUS.data);
endtask
endclass
monitor m;

initial begin
m = new;
m.VBUS = BUS;
BUS.address = 100;
BUS.data    = 1234;
m.disp;
end
endmodule

// Running simulation in ncverilog
// ncverilog +sv virtual_interface.sv

// Running simulation in modelsim/questasim
// vlib work
// vlog -sv virtual_interface.sv
// vsim -c virtual_interface
// run

Download here. system_verilog_virtual_interface

System Verilog OVM – Hello World Program

Here is hello world program in

System Verilog Open Verification Methodology

Download here. hello_ovm

// Filename : hello_ovm.sv

// Author : A.G.Raja

// License : GPL

// Website : https://agraja.wordpress.com

module hello_ovm;

`include “ovm.svh”

class Random extends ovm_transaction;

rand int num;

constraint c { num >= 0 && num < 50; }

function new(string name);

super.new(name);

endfunction

endclass

Random r;

initial begin

r = new(“Hello OVM”);

r.print();

ovm_report_message(“APPLIED ELECTRONICS JOURNAL”,

$psprintf(“Hello World”));

end

endmodule

// End of file hello_ovm.sv

One liner to run this in IUS

When OVM library is not installed by default:

1) Set OVMHOME to the root directory where OVM library is installed

setenv OVMHOME /netstar/ag.raja/sv/OVM/ovm-1.1

2.a) IUS 6.2-s003 and IUS 6.2-s004

irun -sv -nowarn PMBDVX -ovmhome $OVMHOME $OVMHOME/src/ovm_pkg.sv hello_ovm.sv

2.b) IUS 6.2-s005

irun -sv -ovmhome $OVMHOME $OVMHOME/src/ovm_pkg.sv hello_ovm.sv

When OVM is already installed to $CDS_INST_DIR/tools/ovm

a) IUS 6.2-s003 and IUS 6.2-s004

irun -sv -ovm -nowarn PMBDVX hello_ovm.sv

b) IUS 6.2-s005

irun -sv -ovm hello_ovm.sv

Using Options File

irun –f options_file

// options_file begins here

-sv

-ovm

hello_ovm.sv

// options_file ends here

Download here. hello_ovm

System Verilog DPI Example

String passing example

Download as PDF document.

 systemverilogdpi.pdf

1) For illustration strings are used;
But strings can’t be used in module ports;
2) Use SystemVerilog “program” instead of “module” for testbenches.
See this: SystemVerilog program example

//  dpi_top.v
module top ();
import "DPI-C" context v2c_c=
task v2c_sv(input string a);

import "DPI-C" context c2v_c=
function string c2v_sv();

export "DPI-C" print_string_c =
function print_string_sv;

string v2c_string,c2v_string;

function void
print_string_sv(input string aaa);
$display("Exporting VerilogFunction:%s", aaa);
endfunction

initial
begin
v2c_string = "A v2c_string";
v2c_sv(v2c_string);
c2v_string = c2v_sv();
$display("c2v_string: %s n",
c2v_string);
$finish;
end
endmodule

// dpi.h
#include “svdpi.h”

#ifdef __cplusplus
extern “C” {
#endif

extern void print_string_c (const char *_a1);

#ifdef __cplusplus
}
#endif



//  dpi_main.c
#include <stdio.h>
#include "svdpi.h"
#include "dpi.h"
#include "veriuser.h"
void v2c_c(char* v2c_string)
{
io_printf("v2c_string: %sn",v2c_string);
print_string_c("string passed from C");
}
char* c2v_c(void)
{
char* c2v_string;
c2v_string="This is c2v_string";
//io_printf("c2v_string: %sn",
//c2v_string);
return c2v_string;
}
#####   shell script to run simulation
 ncverilog +sv dpi_top.v +elaborate +ncelabargs+-messages
 gcc -fPIC -shared -o dpi_main.so  dpi_main.c  -I/$CDS_INST_DIR/tools.lnx86/inca/include
 ncverilog +sv dpi_top.v +sv_lib=dpi_main.so +access+r +ncsimargs+"-sv_root ./"   
Download NCVerilog demo here.

 systemverilogdpi.pdf

 Here is a demo for running the same example 
using Modelsim under Windows. System Verilog DPI Modelsim Download Modelsim demo here. system-verilog-dpi-modelsim.pdf