System Verilog Virtual Interface

Download here. system_verilog_virtual_interface

// Filename    :
// Author      : A.G.Raja
// License     : GPL
// Website     :

interface bus(input wire clk);
int address;
int data;

modport virtual_interface(input clk);

module virtual_interface;
bit clk;
bus BUS(clk);
class monitor;
virtual bus VBUS;
task disp;
monitor m;

initial begin
m = new;
BUS.address = 100;    = 1234;

// Running simulation in ncverilog
// ncverilog +sv

// Running simulation in modelsim/questasim
// vlib work
// vlog -sv
// vsim -c virtual_interface
// run

Download here. system_verilog_virtual_interface

System Verilog DPI Example

Refer to the previous post for introduction.

System Verilog DPI NCVerilog

The above example gives a demo with NCVerilog.

Here is the run script for running the same example with Modelsim under windows.

Download here. system-verilog-dpi-modelsim.pdf

#File name run.tcl

# Author: A.G.Raja

# Website:

# License: GPL

#Type at Transcript terminal: source run.tcl

vlib work

vlog -sv -dpiheader dpiheader.h dpi_top.v

exec gcc -c -g -IE:/modelsim/include dpi_main.c -o dpi_main.obj

exec gcc -shared -o dpi_main.dll dpi_main.obj -LE:/modelsim/win32

vsim -novopt top -sv_lib dpi_main


# EOF run.tcl

Replace “E:/modelsim” with “modelsim installation path”

1) Don’t create a new project while starting Modelsim

2) Open and proceed directly to Modelsim.

3) At the transcript terminal change to the working directory

4) No need to create a folder named work.

5) The run script given above does it.

Download here. system-verilog-dpi-modelsim.pdf

Download NCVerilog demo here.


Modelsim TCL

Steps for Running a Simulation in Modelsim (Shown for Verilog)

1) Compile all

2) Start Simulation

3) Add Signals to Wave

4) Run

Here’s a TCL script to automate this

# runtb.tcl
vlog dut.v test_bench.v
view wave
vsim work.test_bench_v
add wave -r /*

Save the above file and run from transcript terminal

VSIM 29> source runtb.tcl