Compilation error at UVM factory registration macros

package simple_pkg;

import uvm_pkg::*;

`include “uvm_macros.svh”

class my_class extends uvm_object;


function new(string name=””,int additional_arg);;




The above package seems to be syntactically correct. But compiler(Eg. Cadence irun) throws error.

Compilation error: `uvm_object_utils(my_class). Task/function call, or property/sequence instance does not specify all required formal arguments.

`uvm_object_utils macro tries to register with factory, where the function new doesn’t have additional args.

Compiler throws error due to ‘additional_arg’ to function new. Remove this and compilation error goes off.

Error message is not clear and seems irrelevant to the issue here – a disadvantage of using macros; the macro expands into something that we can’t visualize.


Summary: Avoid additional args to ‘new’ function when using UVM factory registration.




Difference between reg, wire, logic in SystemVerilog


Can be used for input, output, inout

Multiple drivers, No drivers cause x


Wire variable = value;

Assign variable = value;

Can be used to connect module instances



Can be used only for input

Can’t be used in ‘assign’ statement

It takes last assigned value, behaves like a variable


R <= 1;

R <= 0;

R takes value 0, even though there are multiple concurrent assignments



Can be used for input, output. Can’t be used for inout

Can be used in place of wire or reg;

First usage defines the behavior; can’t be changed later.


Assign l = 1; // Valid

Initial l = 1; // Valid

Assign l = 0; initial l = 1; // Invalid



Similar to logic; it is a two state variable.


Non-blocking assignment

No assignment happens to lhs till simulation timestamp is advanced.

Even after #0, the assigned value will not available


Blocking assignment

Lhs gets assigned immediately