Transaction Level Modeling in System Verilog

Download here. transactionlevelmodeling_systemverilog

// Filename    : tlm.sv
// Author      : A.G.Raja
// License     : GPL
// Website     : https://agraja.wordpress.com

module producer_consumer;

virtual class put_if;

// Abstract Class whose methods are not yet implemented
virtual task put(int val);
endtask
endclass

class producer;
put_if put_port;
task run;
int i;
for(i=0;i<10;i++) put_port.put(i);
endtask
endclass

class consumer extends put_if;

// methods of put_if class are over-ridden

// and defined here
task put(int val);
$display(“Consumer receiving “,val);
endtask
endclass

producer p;
consumer c;

initial begin
p = new;
c = new;
p.put_port = c;
p.run;
end
endmodule

// Running simulation in ncverilog

ncverilog +sv tlm.sv

// Running simulation in modelsim/questasim

vlib work

vlog -sv tlm.sv

vsim -c producer_consumer

run

Download here. transactionlevelmodeling_systemverilog

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