Compilation error at UVM factory registration macros

package simple_pkg;

import uvm_pkg::*;

`include “uvm_macros.svh”

class my_class extends uvm_object;

`uvm_object_utils(my_class)

function new(string name=””,int additional_arg);

super.new(name);

endfunction

endclass

endpackage

The above package seems to be syntactically correct. But compiler(Eg. Cadence irun) throws error.

Compilation error: `uvm_object_utils(my_class). Task/function call, or property/sequence instance does not specify all required formal arguments.

`uvm_object_utils macro tries to register with factory, where the function new doesn’t have additional args.

Compiler throws error due to ‘additional_arg’ to function new. Remove this and compilation error goes off.

Error message is not clear and seems irrelevant to the issue here – a disadvantage of using macros; the macro expands into something that we can’t visualize.

 

Summary: Avoid additional args to ‘new’ function when using UVM factory registration.

 

 

SystemVerilog Array of Interfaces

// Viewing Array of interfaces in waveform viewer(dve)

// Notes added inline in the below example

interface my_if(input clk);
logic [31:0] addr;
logic [31:0] data;
endinterface

module dut(input xx, my_if i[1:0], output o, my_if ii);
assign o = xx ? i[0].data : ii.data;
endmodule

module tb;

bit o;
bit clk;

// Array of interface
// Visible where the actual instance is present
// interface signals can’t be seen as arguments of dut
// Visible under ‘tb’, NOT under ‘dut’
my_if i[1:0](clk);

// interface instance – not an array
// Visible under ‘tb’, as well as under ‘dut’
my_if ii(clk);

dut dut(.xx(1’b1), .i (i[1:0]) , .o, .ii);

initial forever #5 clk++;

initial begin
#10
i[0].addr = 10;
i[0].data = ‘hff;
i[1].addr = 20;
i[1].data = ‘haa;
ii.data = 0;
#10
i[0].addr = 110;
i[0].data = ‘h1ff;
i[1].addr = 120;
i[1].data = ‘h1aa;
ii.data = 1;
#100 $finish;
end

// Waveform dumping for VCS
// Change this for other simulators
initial begin
$vcdplusfile(“waves.vpd”);
$vcdpluson;
$vcdplusmemon;
end

endmodule

// Screenshot on waveform viewer (dve)

Interface_Array

General Purpose Preprocessor in Perl

Here is a preprocessor in perl, primarily for Verilog, SystemVerilog, but may be used for any language.
There are programs with a lot of repetitive text. Language features like functions, objects can reduce typing.
Still, there is scope for putting it in lesser code using a text preprocessor.
Limitations in existing preprocessors prompted in writing a new one that addresses the issues
C preprocessor:
Every define has to be written in a single line.
Escape chars for special chars can make the macro unreadable
Very limited keywords. No loop operations
m4 preprocessor:
No escape characters
Difficult to write macros consisting special characters
Advantages of the new preprocessor:
Written in perl, no CPAN packages used, very portable
Very small – 50 lines of code; Only 7 keywords;
No escape characters. Can be used for any programming language.
Possible to emulate features of C-preprocessor as well as m4
Hook to insert perl keywords – shown in example at end of script.
More usage examples coming-up in later posts.
#!/usr/bin/perl
###### General Purpose Preprocessor (c) A.G.Raja ########
my @lines;
my $code;
my $t=0;
my $e;
sub tokenize {
  my $text = shift;
  my @spl  = split(/(\$get\s*\(\s*\w+)\s*\)/,$text);
  my $out  = “”;
  my $var  = “”;
  foreach my $s (@spl) {
    if($s =~ /\$get\s*\((.*)/) {
      $var = $1;
      if($var =~ /^\d+/) {
        $out .= “\$_[$var]”;
      } else { $out .= “\$$var”;
      }
    } else {
      push(@lines,$s);
      $out .= “\$lines[$#lines]”;
    }
  }
  return “\”$out\””;
}
while(<DATA>) {
  s/\$dnl.*\n//;
  if(!length($_)) {
  } elsif(/^\s*\$macro\s+(.*)/) {
    $code .= “\nsub $1 {\n  my \$ret;\n”;
    $t=1;
  } elsif(/^\s*\$endmacro\s*$/) {
    $code .= “return \$ret;\n}\n”;
    $t=0;
  } elsif(/^\s*\$begin\s+(.*)/) {
    $code .= “$1 {\n”;
  } elsif(/^\s*\$end\s*$/) {
    $code .= “}\n”;
  } elsif(/\$set\s+(\$\w+)\s*=(.*)/) {
    $code .= “\n$1 = \”\@{[ $2 ]}\”;\n”;
  } else {
    $e = &tokenize($_);
    if($t==1) {
      $code .= ”  \$ret .= $e;\n”;
    } else {
      $code .= “print $e;\n”;
    }
  }
}
eval $code or die print “\n\n### ERROR: PREPROCESSING FAILED ###\n\n”;
############   TEXT after DATA can be edited   ############
__DATA__
$macro func               $dnl ### This is Start of Macro Definition
$get(0) $dnl              $dnl ### $dnl will Delete-till New-Line
$begin foreach $x (@_)    $dnl ### $begin will append { to perl code
argument is $get(x)       $dnl ##### Substitute perl variable, here $x
$end                      $dnl ### $end will append } to perl code
$endmacro                 $dnl ### This is End of Macro Definition
$set $a = func(1,2,3,4,5) $dnl ### Assign return value of a Macro
aa $begin                 $dnl ### Spaces before keywords not allowed
gadfdasfdas
 $dnl this is a comment. newline+space will be printed here
$get(a)
$dnl ############################################
$dnl #### This Script translates TEXT to perl code and executes it.
$dnl #### Following are Keywords for TEXT to be preprocessed:
$dnl ####   $dnl $macro $endmacro $begin $end $set $get
$dnl #### Usage of the keywords are explained in above example.
$dnl #### $begin keyword can be exploited to get the power of perl.
$dnl ############################################

Difference between reg, wire, logic in SystemVerilog

Wire

Can be used for input, output, inout

Multiple drivers, No drivers cause x

Usage:

Wire variable = value;

Assign variable = value;

Can be used to connect module instances

 

Reg

Can be used only for input

Can’t be used in ‘assign’ statement

It takes last assigned value, behaves like a variable

Note:

R <= 1;

R <= 0;

R takes value 0, even though there are multiple concurrent assignments

 

Logic

Can be used for input, output. Can’t be used for inout

Can be used in place of wire or reg;

First usage defines the behavior; can’t be changed later.

Usage:

Assign l = 1; // Valid

Initial l = 1; // Valid

Assign l = 0; initial l = 1; // Invalid

 

Bit

Similar to logic; it is a two state variable.

 

Non-blocking assignment

No assignment happens to lhs till simulation timestamp is advanced.

Even after #0, the assigned value will not available

 

Blocking assignment

Lhs gets assigned immediately

SystemVerilog Interview Questions

What is the use of OOPs in Verification? Compare Verilog and SV.
OOPs allows plug-and-play re-usable verification components
Verilog – Procedural
SystemVerilog – OOPs. Abstraction, Encapsulation, Inheritance, Polymorphism

Packed Array vs Unpacked Array
Packed array – made of sub-dividing a vector into subfields which can be conveniently accessed as array elements. Also is guaranteed to be represented as a contiguous set of bits. Unpacked array may or many not be so represented.

Usage of arrays
Packed/Unpacked array – Size Known at Compile time
Dynamic array – Size Known at Run-time
Queues – Size Varying at Run-time
Associative array – Index/Key can be random. Sparse Memory Models. Scoreboard for out-of-order transactions

Struct vs. Union
Struct occupies memory of Sum of sizes of all members.
Union occupies memory of Largest sized member. All members point to the same memory location. Tagged Union can declare methods of void type.

Struct vs. Class
Struct can’t have methods. No OOPs ??

Reg vs. Logic
Use logic instead of reg. Intent – deprecate use of reg in future.

Protected vs. Private/Local
Private – Members(fields/methods) can only be accessed within the same scope
Protected – Similar to Private except that Members can be accessed in a derived class

What is polymorphism?
Non-OOP form – Function overloading in C++
OOP form – Dynamic lookup of virtual functions

What is virtual function?
Function which can be over-ridden by extending the class

Use of Packages
Explicit named scope. Similar to namespace in C++
It may contain typedef, variables, functions, sequences and properties

Use of Program Block
Eliminate test-bench race by avoiding non-determinism.
Statements (initial blocks) sensitive to design (module) signals are scheduled in Reactive region.
Initial blocks in modules are scheduled in Active region. Design signals driven from program using non-blocking assignments are updated in NBA region.

Use of Virtual Interface
Separate abstract models from actual signals

System Verilog Singleton Example

Purpose of a singleton:
To have a class which has only one instance(object)
All the objects of this class refer to same global object
that is created only once
This design pattern provides a mechanism for providing
namespaces to global variables

Download here. singleton-design-pattern
C++ example for singleton design pattern: click here

System Verilog example for singleton design pattern

// Filename  : singleton.sv
// Author    : A.G.Raja
// License   : GPL
// Website   : https://agraja.wordpress.com

module tb;

class Singleton;
// object that is created only once
extern static Singleton single;
// constructor that is called only once
extern function new;
// method to get object
extern function Singleton get_instance;
// data to check the functionality
int data;
endclass

initial Singleton::single = null;

function Singleton::new;
data = 14;
endfunction

function Singleton Singleton::get_instance;
// call the constructor for the first time
// if the object has been created already
// return reference to the object already created
if(single==null) single = new;
// return the reference to the object
return single;
endfunction

Singleton s, t;

initial begin
// don’t use s= new;
// since it will create new instances
// instead use the get_instance method
s = s.get_instance();
t = t.get_instance();
$display(“initial value of s.data  = “,s.data);
s.data = 25;
$display(“modified value of s.data = “,s.data);
$display(“value of t.data          = “,t.data);
end
endmodule

Result:
initial value of s->data  = 14
modified value of s->data = 25
value of t->data          = 25
Download here. singleton-design-pattern

System Verilog Virtual Interface

Download here. system_verilog_virtual_interface

// Filename    : virtual_interface.sv
// Author      : A.G.Raja
// License     : GPL
// Website     : https://agraja.wordpress.com

interface bus(input wire clk);
int address;
int data;

modport virtual_interface(input clk);
endinterface

module virtual_interface;
bit clk;
bus BUS(clk);
class monitor;
virtual bus VBUS;
task disp;
$display(VBUS.address);
$display(VBUS.data);
endtask
endclass
monitor m;

initial begin
m = new;
m.VBUS = BUS;
BUS.address = 100;
BUS.data    = 1234;
m.disp;
end
endmodule

// Running simulation in ncverilog
// ncverilog +sv virtual_interface.sv

// Running simulation in modelsim/questasim
// vlib work
// vlog -sv virtual_interface.sv
// vsim -c virtual_interface
// run

Download here. system_verilog_virtual_interface