SystemVerilog Interview Questions

What is the use of OOPs in Verification? Compare Verilog and SV.
OOPs allows plug-and-play re-usable verification components
Verilog – Procedural
SystemVerilog – OOPs. Abstraction, Encapsulation, Inheritance, Polymorphism

Packed Array vs Unpacked Array
Packed array – made of sub-dividing a vector into subfields which can be conveniently accessed as array elements. Also is guaranteed to be represented as a contiguous set of bits. Unpacked array may or many not be so represented.

Usage of arrays
Packed/Unpacked array – Size Known at Compile time
Dynamic array – Size Known at Run-time
Queues – Size Varying at Run-time
Associative array – Index/Key can be random. Sparse Memory Models. Scoreboard for out-of-order transactions

Struct vs. Union
Struct occupies memory of Sum of sizes of all members.
Union occupies memory of Largest sized member. All members point to the same memory location. Tagged Union can declare methods of void type.

Struct vs. Class
Struct can’t have methods. No OOPs ??

Reg vs. Logic
Use logic instead of reg. Intent – deprecate use of reg in future.

Protected vs. Private/Local
Private – Members(fields/methods) can only be accessed within the same scope
Protected – Similar to Private except that Members can be accessed in a derived class

What is polymorphism?
Non-OOP form – Function overloading in C++
OOP form – Dynamic lookup of virtual functions

What is virtual function?
Function which can be over-ridden by extending the class

Use of Packages
Explicit named scope. Similar to namespace in C++
It may contain typedef, variables, functions, sequences and properties

Use of Program Block
Eliminate test-bench race by avoiding non-determinism.
Statements (initial blocks) sensitive to design (module) signals are scheduled in Reactive region.
Initial blocks in modules are scheduled in Active region. Design signals driven from program using non-blocking assignments are updated in NBA region.

Use of Virtual Interface
Separate abstract models from actual signals


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