PCI Express

One PCIe lane consists of a differential Tx pair, Rx pair. One PCIe link consists at-least one lane. An xN link denotes N lanes. Supported link widths: x1, x2, x4, x8, x16, x32.

Raw Bandwidth: 2.5Gbps/lane/direction.

During hardware initialization, each PCI Express Link is set up following a negotiation of Lane widths and frequency of operation by the two agents at each end of the Link. No firmware or operating system software is involved.

A PCIe fabric consists of point-to-point links that interconnect a set of components. Root complex at the top of the hierarchy connects CPU/memory subsystem to the I/O (End-point device, switch, PCIe-PCI bridge, etc). Each of the components is mapped in a single flat address space and can be accessed using PCI-like load/store accesses transaction semantics.


Load-store mechanism in PCI:
From the CPU’s perspective, PCI devices are accessible via a fairly straightforward load-store mechanism. There’s flat, unified chunk of address space dedicated for PCI use, which looks to the CPU much like a flat chunk of main memory address space, the primary difference being that at each range of addresses there sits a PCI device instead of a group of memory cells containing code or data. When a PCI-enabled computer boots up, it must initialize the PCI subsystem by assigning chunks of the PCI address space to the different devices so that they’ll be accessible to the CPU.


PCI Express’s designers have left this load-store-based, flat memory model unchanged. So a legacy application that wants to communicate via PCIe still executes a read from or a write to a specific address. Hence PCIe is backwards-compatible with PCI, and that operating systems can boot on and use a PCIe-based system without modification.

Note: In PCI system, devices are connected to host (root) through a shared bus (parallel bus). There is an arbitration scheme that decides who gets access to the bus. In PCIe system, devices are connected to root complex by point-to-point connection (serial connection).


PCI Express uses packets to communicate information between components.
The capability to route peer-to-peer transactions between hierarchy domains through a Root Complex is optional and implementation dependent. For example, an implementation may incorporate a real or virtual Switch internally within the Root Complex to enable full peer-to-peer support in a software transparent way.

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One thought on “PCI Express

  1. In your artical you say that operating systems can boot on and use a PCIe-based system – what BIOs configuration/ chipset or mother board is required and what registers are used to boot from the PCIe device? What is required to boot from the PCIe device?

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