JTAG

JTAG: Joint Test Action Group

Boundary Scan technology has the ability to set and read values on pins without direct physical access. Boundary Scan Register: Intercepts device’s core logic and its pins which is invisible for normal operation. In test mode these cells can be used to set/read values.

TCK: Test ClocK synchronizes the internal state machine operations

TMS: Test Mode State’ is sampled at the rising edge of TCK to determine the next state.

TDI: Test Data In represents the data shifted into the device’s test or programming logic. It is sampled at the rising edge of TCK when the internal state machine is in the correct state.

TDO: Test Data Out represents the data shifted out of the device’s test or programming logic and is valid on the falling edge of TCK when the internal state machine is in the correct state.

TRST: Test Reset is an optional pin which, when available, can reset the TAP controller’s state machine.

Instruction Register: Defines to which of the data registers signals should be passed.

Data Registers:

BSR- Boundary Scan Register: The main testing data register used to move data to and from the ‘pins’ on a device.

BYPASS Register: A single-bit register that passes information from TDI to TDO.

IDCODES Register: Contains the ID code and revision number for the device. This information allows the device to be linked to its Boundary Scan Description Language (BSDL) file.

The IEEE 1149.1 standard defines a set of instructions that must be available for a device to be considered compliant.


TAP (Test Access Port) controller:
A state machine whose transitions are controlled by TMS signal. All states have two exits (for TMS=0, TMS=1). Two main paths (in the state machine) allow for setting or retrieving information from either a data register or the instruction register on the device. The data register operated on (e.g. BSR, IDCODES, BYPASS) depends on the value loaded into the instruction register.

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