The SPI-bus is a 4-wire serial communications interface used by many microprocessor peripheral chips. The Serial Peripheral Interface (SPI) circuit is a synchronous serial data link that is standard across many Motorola microprocessors and other peripheral chips. It provides support for a low/medium bandwidth (1 megabaud) network connection amongst CPUs and other devices supporting the SPI.
SPI bus is basically a relatively simple synchronous serial interface for connecting low speed external devices using quite minimal number of wires. SPI (serial peripheral interface) is an interface standard defined by Motorola on the MC68HCxx line of microcontrollers. A synchronous clock shifts serial data into and out of the microcontrollers in blocks of 8 bits. SPI – Serial Peripheral Interface. SPI is used frequently in handheld and other mobile platform systems.
SPI bus is a master/slave interface. Whenever two devices communicate, one is referred to as the “master” and the other as the “slave” device. The master drives the serial clock. When using SPI, data is simultaneously transmitted and received, making it a full-duplexed protocol.
Motorola’s names for the signals are as follows: SCLK for serial clock, which is always driven by the master: MISO is master-in slave-out data: MOSI is master-out slave-in data. In a typical application, connect the microcontroller’s SCLK to the converter’s SCLK input, connect the MISO to the converter’s DOUT pin, and connect the MOSI pin to the converter’s DIN pin. Serial protocols such as SPI, a chip-select input is required to enable the IC. Using this chip-select signal it is possible to connect many ICs to same SPI bus in parallel. If there is a chip-select (CS) signal in use, it can be driven by a spare microcontroller general-purpose output. Every IC connected to bus needs it’s own chip-select signal line. Thus, when 10 devices are on the bus, 10 chip-select lines, in addition to the shared clock and data lines, are needed to select the appropriate device.
The SPI interface is based on a 8 bit shift register. The shift clock (SCK) is provided by the master device. SCK is a gated clock and is only generated during shifting. SCK stays idle between transfers. Transmitting and receiving occurs simultaneously: While the master shifts out it’s transmit data, data from the slave is shifted in. As a result, the master must always send data in order to generate clocks, even if only data reception is required. The following diagram shows a basic interface and a sample data transfer: Data on SDO is shifted out with the falling SCK edge; data on SDI is sampled on the rising SCK edge. The SCK idle polarity is ‘High’.