I2S bus


I2S = Inter IC Sound

*Serial bus designed for digital audio devices
*Developed by Philips
*Typical clock 2.5 MHz, Maximum clock speed 3.125 MHz


SCK: Continuous Serial Clock

WS : Word Select

SD : Serial Data

Device generating SCK, WS is the master

TTL logic levels

VOL < 0.4V

VOH > 2.4V

VIL = 0.8V

VIH = 2.0V

IIL = -15mA

IIH = 0.04mA

Operation: Serial data is transmitted in two’s complement with the MSB first (one clock period after the WS changes).Transmitter and Receiver may have different word lengths(Word length adjustable upto 28 bits).If receiver is sent more bits than its word length, bits after its LSB are ignored. If receiver is sent fewer bits than its word length, missing bits are set to zero internally.i2s_bus.JPGTransmitter essentially consists a parallel to serial shift register.SCK defines the data rate. SD is the serial data out from the shift register.WS: The number of clock cycles it is asserted, defines the transmitter word length.Receiver essentially consists a serial to parallel converter.A counter is used at the receiver to count the number of cycles WS is assertedto find the transmitted word length.


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