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Posts Tagged ‘PCB design’

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Open Drain Lines

In Uncategorized on February 6, 2007 at 12:38 am

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EBD file simulation

In Uncategorized on January 31, 2007 at 12:32 am

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IBIS cookbook

In Uncategorized on January 26, 2007 at 12:29 am

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Data Acquisition

In Uncategorized on January 12, 2007 at 12:38 am

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SketchUp Electronic Components

In Uncategorized on December 23, 2006 at 12:37 am

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Logic Families Voltage Translation

In Uncategorized on December 21, 2006 at 10:03 am

No Translation required for the following:

[TTL] to [TTL]

[TTL] to [CMOS with input switching at TTL levels]

[CMOS 5V] to [TTL]

 

 

Translation required for the following:

[TTL] to [CMOS*]

            Pull up of 1k to 2k required

            TTL outputs 2.4V to 3.3V for a high level

            CMOS required 3.7 for high level.

            The pull up resister increases the output voltage (of TTL driver).

 

[CMOS*] to [TTL]

 

*The translation depends on the VCC of CMOS device.

 

 

[TTL] to [ECL]  /   [ECL] to [TTL]

            TTL to ECL (ECL to TTL) translator along with ECL termination resistors are needed.

 

[PECL] to [TTL]  /  [TTL] to [PECL]

            PECL is Positive ECL

            PECL to TTL (TTL to PECL) translator needed.

[PECL] to [CMOS]  /  [CMOS] to [PECL]

            Same as above, but pull of 1k to 2k is required for CMOS.

 

 

[PECL 5V] to [LVDS 5V]

            Pull up both +,- signals to 3V through 50E resistors.

 

[LVPECL 3.3V] to [LVDS 5V]

            Pull up both +,- signals to 1.3V through 50E resistors

 

 

 

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Signal Integrity Principles

In Uncategorized on December 21, 2006 at 7:23 am

Each interconnect is a transmission line

Forget the word ground; Think return path.

Bandwidth of a signal is the highest sine wave frequency component.

All SI formulas are definitions or approximations.

 

Even a two inch long trace on a PCB can affect SI.

 

SI problems: Timing, Noise, EMI

Noise sources:

Signal on a net: Reflections, Distortions from Impedance discontinuities

Crosstalk: Mutual Inductance, Mutual (parasitic) capacitance

Rail collapse: Voltage drop in power/ground.

EMI: A component or entire system

 

Impedance discontinuities: Cross section, topology, added components(via, connector, etc.)

 

Ways to minimize cross talk (cross talk should kept as minimum as 5%)

1) Use uniform plane as return path.

2) Spacing traces farther apart.

3) Use guard traces.

 

Rail-Collapse noise (Rail-bounce, Ground bounce):

Because of the impedance of the power and ground distribution, a voltage drop will occur as the IC current switches. This voltage drop means the power and ground rails have collapsed from their nominal values.

Simultaneous switching noise (SSN) or simultaneous switching output (SSO): Whenever an output pin changes state, the current it draws from its ICs 0V and power rails eventually flows through the interconnections to the PCB’s 0V and power rails. The inductance in these paths causes voltage drops that make the IC’s internal 0V and power rails ‘bounce’ with respect to the PCB rails, according to the activity of the output ports

Ways to minimize:

1) Closely placed power-ground planes with thin dielectric

2) Low inductance decaps, on-chip decaps

3) Multiple short power, ground pins in packages

 

Sources of EMI

1) Conversion of some differential signal into a common signal

2) Ground bounce

Ways to minimize:

1) Use shielded cables

2) Use low-impedance connections

 

Rise time: Time taken to go from 10% to 90% of the final value.

Mostly rise time is about 10% of clock period.

 

Bandwidth = 0.35*[Rise Time]

For most microprocessor, ASIC based systems rise time is 7% of clock period.

Approximately bandwidth is five times the clock frequency.

 

An electron travels (in a copper wire) at a speed of 1cm/s.

Time to travel down a 6” of interconnect in FR4 is about 1ns.

 

 

 

 

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USB – Universal Serial Bus

In Uncategorized on December 19, 2006 at 12:52 pm

USB is a polled cable bus with single-host-scheduled, token-based protocol.

Tiered-star topology: USB host is the root hub. A hub is center of a star. A star consists of point-to-point connections between [host and hub/function] or [hub and (another) hub/function].

Allowed topology: Maximum tiers = 7; Maximum non-root hubs in a tier = 5.

Data rates:

High-speed: 480 Mbps

Full-speed: 12 Mbps

Low-speed: 1.5Mbps

For effective utilization of bandwidth, full-speed and low-speed data can be transmitted at high-speed between host and hub, but transmitted between hub and device at full-speed or low-speed.

Operation: Clock is transmitted, encoded (NRZI encoding with bit stuffing) with differential data. A SYNC field precedes each packet for synchronization. The cable also carries VBUS (+5V at source) and GND to deliver power to devices. Cable with biased terminations at each end and up to seven metre length is allowed.

Most bus transactions involve the transmission of up to three packets. Each transaction begins when the Host Controller, on a scheduled basis, sends a USB packet describing the type and direction of transaction, the USB device address, and endpoint number. This packet is referred to as the “token packet.” The USB device that is addressed selects itself by decoding the appropriate address fields. In a given transaction, data is transferred either from the host to a device or from a device to the host. The direction of data transfer is specified in the token packet. The source of the transaction then sends a data packet or indicates it has no data to transfer. The destination, in general, responds with a handshake packet indicating whether the transfer was successful.

Some bus transactions between host controllers and hubs involve the transmission of four packets. These types of transactions are used to manage the data transfers between the host and full-/low- speed devices. The USB data transfer model between a source or destination on the host and an endpoint on a device is referred to as a pipe. There are two types of pipes: stream and message. Stream data has no USB-defined structure, while message data does. Additionally, pipes have associations of data bandwidth, transfer service type, and endpoint characteristics like directionality and buffer sizes. Most pipes come into existence when a USB device is configured. One message pipe, the Default Control Pipe, always exists once a device is powered, in order to provide access to the device’s configuration, status, and control information.

The transaction schedule allows flow control for some stream pipes. At the hardware level, this prevents buffers from under-run or overrun situations by using a NAK handshake to throttle the data rate. When NAKed, a transaction is retried when bus time is available. The flow control mechanism permits the construction of flexible schedules that accommodate concurrent servicing of a heterogeneous mix of stream pipes. Thus, multiple stream pipes can be serviced at different intervals and with packets of different sizes.

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UART

In Uncategorized on December 19, 2006 at 11:43 am

Universal Asynchronous Receiver Transmitter: Used for serial communications via cable.  UART generates signals of same timing as RS-232 used by Personal Computer’s COM ports. 

Standard

Logic 0

Logic 1

UART

0V

5V

RS-232

+12V

-12V

 
Asynchronous communication requires clock recovery, where a known transition event in the data is used to synchronize transmitter/receiver.

Baud rate of UART: integer multiples or submultiples of 9600 Hz.

RS-232 frame:

1) Start bit (always logic 0)

2) Data bits (5, 6, 7, or 8 of them)

3) A parity bit (optional, even or odd parity)

4) A stop bit (always logic 1); may be 1, 1.5, 2 bit times in duration

 
The synchronization point is at the start of the frame (always a 1 to 0 transition).

• The 8 received data values are sampled 1.5BT, 2.5BT, … , 8.5BT after the synchronization point (BT = bit time).

• The stop bit is sampled 9.5BT after the synchronization point (if it is not a logic 1, this is a framing error).

Send, Receive data are buffered using Tx, Rx registers.

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JTAG

In Uncategorized on December 19, 2006 at 11:05 am

JTAG: Joint Test Action Group

Boundary Scan technology has the ability to set and read values on pins without direct physical access. Boundary Scan Register: Intercepts device’s core logic and its pins which is invisible for normal operation. In test mode these cells can be used to set/read values.

TCK: Test ClocK synchronizes the internal state machine operations

TMS: Test Mode State’ is sampled at the rising edge of TCK to determine the next state.

TDI: Test Data In represents the data shifted into the device’s test or programming logic. It is sampled at the rising edge of TCK when the internal state machine is in the correct state.

TDO: Test Data Out represents the data shifted out of the device’s test or programming logic and is valid on the falling edge of TCK when the internal state machine is in the correct state.

TRST: Test Reset is an optional pin which, when available, can reset the TAP controller’s state machine.

Instruction Register: Defines to which of the data registers signals should be passed.

Data Registers:

BSR- Boundary Scan Register: The main testing data register used to move data to and from the ‘pins’ on a device.

BYPASS Register: A single-bit register that passes information from TDI to TDO.

IDCODES Register: Contains the ID code and revision number for the device. This information allows the device to be linked to its Boundary Scan Description Language (BSDL) file.

The IEEE 1149.1 standard defines a set of instructions that must be available for a device to be considered compliant.


TAP (Test Access Port) controller: A state machine whose transitions are controlled by TMS signal. All states have two exits (for TMS=0, TMS=1). Two main paths (in the state machine) allow for setting or retrieving information from either a data register or the instruction register on the device. The data register operated on (e.g. BSR, IDCODES, BYPASS) depends on the value loaded into the instruction register.

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Online Simulations

In Uncategorized on December 14, 2006 at 12:37 am

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1U

In Uncategorized on December 5, 2006 at 5:45 am

U is unit of measure for vertical usable space, or height of racks, cabinets. 1U is equal to 1.75 inches (44.45mm).

Example : Form-factor of 3U cPCI board is 100mm x 160mm

Form-factor of 6U cPCI board is 100mm x 233.35mm

Note: 3U as per the definition is 3 x 44.45 mm = 133.35. But 160mm is defined in the cPCI specifications.

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Simulation resources

In Uncategorized on December 2, 2006 at 12:43 am

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PCI – Peripheral Component Interconnect

In Uncategorized on November 30, 2006 at 11:47 am

 

All signals except Reset, Interrupt are sampled at rising edge of clock.

Operation:
A bus transaction is followed by an address phase followed by one or more data phases. Address phase starts when FRAME# is asserted. For read operation TRDY#(target ready) is asserted. For write operation IRDY#(initiator ready) is asserted. Data phase completes on any clock both IRDY#, TRDY# are asserted. Wait cycles are inserted until both are asserted together.

Address, Data pins are multiplexed. C/BE# pins are multiplexed. They define bus command for address phase, byte enable for data phase. STOP# signal indicates the current target is requesting the master to stop the current transaction. LOCK# used for atomic operations. IDSEL (Initialization Device select) used as chip select for configuration read, write transactions. DEVSEL# indicates whether any device on the bus is selected. Arbitration signals (REQ#, GNT#) of bus master: request, grant access to bus provided RST# is de-asserted.

PAR – even parity signal; has same timing of address/data but delayed by one clock. PAR is driven by master for address, write data phases, and by slave for read data phases. PERR#, SERR# report data parity error, system error(address/command) respectively. M66EN indicates 33MHz or 66MHz. ACK64# acknowledges 64 bit transfer.

Optional Signals:
INTA#, INTB#, INTC#, INTD# — request interrupt. PRSNT indicates the motherboard presence of add-in board. CLKRUN# indicates status of CLK. PME — asynchronous signal used to request a change is system power state. 3.3VAUX — auxiliary power source. TCK, TDI, TDO, TMS, TRST# — JTAG signals

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PCB Layout

In Uncategorized on November 25, 2006 at 12:27 am

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SPI interface

In Bookmarks on November 22, 2006 at 9:40 am

 

spi.JPG

 

The SPI-bus is a 4-wire serial communications interface used by many microprocessor peripheral chips. The Serial Peripheral Interface (SPI) circuit is a synchronous serial data link that is standard across many Motorola microprocessors and other peripheral chips. It provides support for a low/medium bandwidth (1 megabaud) network connection amongst CPUs and other devices supporting the SPI.

SPI bus is basically a relatively simple synchronous serial interface for connecting low speed external devices using quite minimal number of wires. SPI (serial peripheral interface) is an interface standard defined by Motorola on the MC68HCxx line of microcontrollers. A synchronous clock shifts serial data into and out of the microcontrollers in blocks of 8 bits. SPI – Serial Peripheral Interface. SPI is used frequently in handheld and other mobile platform systems.

SPI bus is a master/slave interface. Whenever two devices communicate, one is referred to as the “master” and the other as the “slave” device. The master drives the serial clock. When using SPI, data is simultaneously transmitted and received, making it a full-duplexed protocol.

Motorola’s names for the signals are as follows: SCLK for serial clock, which is always driven by the master: MISO is master-in slave-out data: MOSI is master-out slave-in data. In a typical application, connect the microcontroller’s SCLK to the converter’s SCLK input, connect the MISO to the converter’s DOUT pin, and connect the MOSI pin to the converter’s DIN pin. Serial protocols such as SPI, a chip-select input is required to enable the IC. Using this chip-select signal it is possible to connect many ICs to same SPI bus in parallel. If there is a chip-select (CS) signal in use, it can be driven by a spare microcontroller general-purpose output. Every IC connected to bus needs it’s own chip-select signal line. Thus, when 10 devices are on the bus, 10 chip-select lines, in addition to the shared clock and data lines, are needed to select the appropriate device.

 

 

The SPI interface is based on a 8 bit shift register. The shift clock (SCK) is provided by the master device. SCK is a gated clock and is only generated during shifting. SCK stays idle between transfers. Transmitting and receiving occurs simultaneously: While the master shifts out it’s transmit data, data from the slave is shifted in. As a result, the master must always send data in order to generate clocks, even if only data reception is required. The following diagram shows a basic interface and a sample data transfer: Data on SDO is shifted out with the falling SCK edge; data on SDI is sampled on the rising SCK edge. The SCK idle polarity is ‘High’.

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Eye Diagram

In Uncategorized on November 22, 2006 at 8:45 am

eye-diagram.JPG
By super-imposing the transition patterns of a signal for 011, 001, 100, 110,
we get an Eye-Diagram. This is used to study Jitter, Voltage swing and Transition time.
The above diagram shows perfect one, practical one respectively.

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VME protocol

In Uncategorized on November 16, 2006 at 9:33 am

The master puts address onto the bus, delays a minimum of 35ns, and then asserts address strobe.  All slave cards on the bus monitor the addresses. Each slave is set up to decode a unique address.  For a write operation, the master asserts one or both of its data strobes.  The assertion of data strobe tells the slave that data is valid on the bus and can be strobed into memory. The slave then asserts data acknowledge to signal that the data has been captured.

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Characteristic Impedance of Micro-strip line

In Uncategorized on November 16, 2006 at 9:31 am

Z0=[L/C]^(1/2)= 377(h/w)[Er^{-1/2)]

Er=Relative permittivity of the dielectric material

h = thickness of dielectric

w = trace width

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PCB Design Tips

In Uncategorized on November 8, 2006 at 12:43 am

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Thumb rule to calculate via inductance

In Uncategorized on November 7, 2006 at 3:46 am

L=5.08h[ln{4h/d)+1] Unit: nH
ln –> natural logarithm
h — > via length (PCB thickness) Unit: inch
d — > via diameter in inches Unit: inchL=5.08h[ln{4h/d)+1] Unit: nH
ln –> natural logarithm
h — > via length (PCB thickness) Unit: inch
d — > via diameter in inches Unit: inch

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Reflections on a transmission line

In Uncategorized on November 7, 2006 at 3:43 am

On a long straight line, waves can travel in both directions. Consider a
mechanical transmission line suspended vertically and hung from the
ceiling. Reflections is seen by setting off a pulse from the bottom of
the line. After a time equal to twice the transit time, the pulse
reflects from the ceiling and returns to your hand. This takes a few
seconds. The pulse has been reflected at the top because the line is
anchored there at zero displacement for all time. In an electronic
transmission line, this is equivalent to holding the voltage at zero for
all time by using a short circuit across the line. If you look at the
direction of displacement in the pulse, it reverses on reflection. Thus,
a wave of displacement to the right is returned as a wave of
displacement to the left. In an electronic transmission line, a square
pulse of 1 volt amplitude is returned as a square pulse of -1 volt
amplitude.

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Relative Dielectric Constants

In Uncategorized on October 9, 2006 at 9:53 am
Material Er
Air 1.0
PTFE/glass 2800 2.2
Rogers RO 2.9
CE/goreply 3.0
BT/goreply 3.3
GETEK 3.5
CE/glass 3.7
Silicon dioxide 3.9
BT/glass 4.0
Polymide/glass 4.1
FR-4/glass 4.1
Glass cloth 6.0
Alumina 9.0