Electronics « Applied Electronics Journal

Because of the impedance of the power and ground distribution, a voltage drop will occur as the IC current switches. This voltage drop means the power and ground rails have collapsed from their nominal values.

Simultaneous switching noise (SSN) or simultaneous switching output (SSO): Whenever an output pin changes state, the current it draws from its ICs 0V and power rails eventually flows through the interconnections to the PCB’s 0V and power rails. The inductance in these paths causes voltage drops that make the IC’s internal 0V and power rails ‘bounce’ with respect to the PCB rails, according to the activity of the output ports

Ways to minimize:

1) Closely placed power-ground planes with thin dielectric

2) Low inductance decaps, on-chip decaps

3) Multiple short power, ground pins in packages

Sources of EMI

1) Conversion of some differential signal into a common signal

2) Ground bounce

Ways to minimize:

1) Use shielded cables

2) Use low-impedance connections

Rise time: Time taken to go from 10% to 90% of the final value.

Mostly rise time is about 10% of clock period.

Bandwidth = 0.35*[Rise Time]

For most microprocessor, ASIC based systems rise time is 7% of clock period.

Approximately bandwidth is five times the clock frequency.

An electron travels (in a copper wire) at a speed of 1cm/s.

Time to travel down a 6” of interconnect in FR4 is about 1ns.

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Electronics, Formula

Ideal Square Wave

In Uncategorized on December 21, 2006 at 6:39 am

Duty cycle = 50%

Peak value = 1 V

Frequency = 1 GHz

Amplitude of nth harmonic An = 2/(n*pi)

All even harmonics are zero.

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Electronics, Formula

Self inductance of circular loop of wire

In Uncategorized on December 21, 2006 at 6:28 am

L = 32*R*ln(4R/D) nH

where R = radius of loop in inches

D = diameter of wire in inches

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Communication, Electronics, Networking

PCI Express

In Uncategorized on December 19, 2006 at 7:39 am

One PCIe lane consists of a differential Tx pair, Rx pair. One PCIe link consists at-least one lane. An xN link denotes N lanes. Supported link widths: x1, x2, x4, x8, x16, x32.

Raw Bandwidth: 2.5Gbps/lane/direction.

During hardware initialization, each PCI Express Link is set up following a negotiation of Lane widths and frequency of operation by the two agents at each end of the Link. No firmware or operating system software is involved.

A PCIe fabric consists of point-to-point links that interconnect a set of components. Root complex at the top of the hierarchy connects CPU/memory subsystem to the I/O (End-point device, switch, PCIe-PCI bridge, etc). Each of the components is mapped in a single flat address space and can be accessed using PCI-like load/store accesses transaction semantics.

Load-store mechanism in PCI: From the CPU’s perspective, PCI devices are accessible via a fairly straightforward load-store mechanism. There’s flat, unified chunk of address space dedicated for PCI use, which looks to the CPU much like a flat chunk of main memory address space, the primary difference being that at each range of addresses there sits a PCI device instead of a group of memory cells containing code or data. When a PCI-enabled computer boots up, it must initialize the PCI subsystem by assigning chunks of the PCI address space to the different devices so that they’ll be accessible to the CPU.

PCI Express’s designers have left this load-store-based, flat memory model unchanged. So a legacy application that wants to communicate via PCIe still executes a read from or a write to a specific address. Hence PCIe is backwards-compatible with PCI, and that operating systems can boot on and use a PCIe-based system without modification.

Note: In PCI system, devices are connected to host (root) through a shared bus (parallel bus). There is an arbitration scheme that decides who gets access to the bus. In PCIe system, devices are connected to root complex by point-to-point connection (serial connection).

PCI Express uses packets to communicate information between components. The capability to route peer-to-peer transactions between hierarchy domains through a Root Complex is optional and implementation dependent. For example, an implementation may incorporate a real or virtual Switch internally within the Root Complex to enable full peer-to-peer support in a software transparent way.

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Communication, Electronics, Formula, Networking, PCB design

1U

In Uncategorized on December 5, 2006 at 5:45 am

U is unit of measure for vertical usable space, or height of racks, cabinets. 1U is equal to 1.75 inches (44.45mm).

Example : Form-factor of 3U cPCI board is 100mm x 160mm

Form-factor of 6U cPCI board is 100mm x 233.35mm

Note: 3U as per the definition is 3 x 44.45 mm = 133.35. But 160mm is defined in the cPCI specifications.

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Communication, Electronics, Networking, PCB design

PCI – Peripheral Component Interconnect

In Uncategorized on November 30, 2006 at 11:47 am

All signals except Reset, Interrupt are sampled at rising edge of clock.

Operation:
A bus transaction is followed by an address phase followed by one or more data phases. Address phase starts when FRAME# is asserted. For read operation TRDY#(target ready) is asserted. For write operation IRDY#(initiator ready) is asserted. Data phase completes on any clock both IRDY#, TRDY# are asserted. Wait cycles are inserted until both are asserted together.

Address, Data pins are multiplexed. C/BE# pins are multiplexed. They define bus command for address phase, byte enable for data phase. STOP# signal indicates the current target is requesting the master to stop the current transaction. LOCK# used for atomic operations. IDSEL (Initialization Device select) used as chip select for configuration read, write transactions. DEVSEL# indicates whether any device on the bus is selected. Arbitration signals (REQ#, GNT#) of bus master: request, grant access to bus provided RST# is de-asserted.

PAR – even parity signal; has same timing of address/data but delayed by one clock. PAR is driven by master for address, write data phases, and by slave for read data phases. PERR#, SERR# report data parity error, system error(address/command) respectively. M66EN indicates 33MHz or 66MHz. ACK64# acknowledges 64 bit transfer.

Optional Signals:
INTA#, INTB#, INTC#, INTD# — request interrupt. PRSNT indicates the motherboard presence of add-in board. CLKRUN# indicates status of CLK. PME — asynchronous signal used to request a change is system power state. 3.3VAUX — auxiliary power source. TCK, TDI, TDO, TMS, TRST# — JTAG signals

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Communication, Electronics, Images, Networking, Tips and Tricks

OSI Reference Model – Easy way to remember

In Bookmarks on November 27, 2006 at 11:24 am

Application Layer: End user processes like file transfer, e-mail, network software services. E.g. Telnet, FTP

Presentation/Syntax Layer: Format, Encrypt data to send across network.

Session Layer: Establishes, manages and terminates connections between applications .

Transport Layer: End-to-end error recovery, flow control.

Network Layer: Switching, Routing, Addressing, internetworking, error handling, congestion control and packet sequencing.

Data Link Layer: Encoding, decoding data packets into bits.

Media Access Control Sub-layer: Data access/transmit permissions.

Logical Link Sub-layer: Frame synchronization, flow control, error checking.

Physical Layer: Conveys the bit stream (electrical, light, radio)

E.g. Ethernet, RS232, ATM

An easy way to remember : use the following quotes

“All People Seem To Need Data Processing”

“People Do Not Trust Sales People Always”

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Electronics, Products, Study, Usenet

Electronic Component Search

In Uncategorized on November 23, 2006 at 12:36 am

· Freescale Dual G4 MPC7457 Processor board

Freescale Dual G4 MPC7457 Development Board

(tags: Freescale Dual G4 MPC7457 Development Board)

· European Telecommunication Standards Institute

European Telecommunication Standards Institute

(tags: European Telecommunication Standards Institute DVB satellite communication electronics)

· Acqutek – Backplane Boards

isa picmg pciisa backplane board manufacturer

(tags: vendors backplane picmg isa eisa pciisa board pcb-design pci)
Collected Quotes from Albert Einstein

Anyone who has never failed has never tried anything new

(tags: Albert Einstein quotes great philosophy)
ProProfs.com Educational FREEway by Professionals & Professors

Free webschools

(tags: webschool school tutorial certification free education ebooks)
Einstein writes your words

Make Einstein write your words.
Then save the dynamically generated picture

(tags: Einstein picture images quote)
Electronic Component Search

Google Co-op – Custom Search Engine

(tags: search google co-op agrajame custom electronics part)

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Communication, Electronics, PCB design

SPI interface

In Bookmarks on November 22, 2006 at 9:40 am

The SPI-bus is a 4-wire serial communications interface used by many microprocessor peripheral chips. The Serial Peripheral Interface (SPI) circuit is a synchronous serial data link that is standard across many Motorola microprocessors and other peripheral chips. It provides support for a low/medium bandwidth (1 megabaud) network connection amongst CPUs and other devices supporting the SPI.

SPI bus is basically a relatively simple synchronous serial interface for connecting low speed external devices using quite minimal number of wires. SPI (serial peripheral interface) is an interface standard defined by Motorola on the MC68HCxx line of microcontrollers. A synchronous clock shifts serial data into and out of the microcontrollers in blocks of 8 bits. SPI – Serial Peripheral Interface. SPI is used frequently in handheld and other mobile platform systems.

SPI bus is a master/slave interface. Whenever two devices communicate, one is referred to as the “master” and the other as the “slave” device. The master drives the serial clock. When using SPI, data is simultaneously transmitted and received, making it a full-duplexed protocol.

Motorola’s names for the signals are as follows: SCLK for serial clock, which is always driven by the master: MISO is master-in slave-out data: MOSI is master-out slave-in data. In a typical application, connect the microcontroller’s SCLK to the converter’s SCLK input, connect the MISO to the converter’s DOUT pin, and connect the MOSI pin to the converter’s DIN pin. Serial protocols such as SPI, a chip-select input is required to enable the IC. Using this chip-select signal it is possible to connect many ICs to same SPI bus in parallel. If there is a chip-select (CS) signal in use, it can be driven by a spare microcontroller general-purpose output. Every IC connected to bus needs it’s own chip-select signal line. Thus, when 10 devices are on the bus, 10 chip-select lines, in addition to the shared clock and data lines, are needed to select the appropriate device.

The SPI interface is based on a 8 bit shift register. The shift clock (SCK) is provided by the master device. SCK is a gated clock and is only generated during shifting. SCK stays idle between transfers. Transmitting and receiving occurs simultaneously: While the master shifts out it’s transmit data, data from the slave is shifted in. As a result, the master must always send data in order to generate clocks, even if only data reception is required. The following diagram shows a basic interface and a sample data transfer: Data on SDO is shifted out with the falling SCK edge; data on SDI is sampled on the rising SCK edge. The SCK idle polarity is ‘High’.

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Communication, Electronics, Images, PCB design

Eye Diagram

In Uncategorized on November 22, 2006 at 8:45 am

By super-imposing the transition patterns of a signal for 011, 001, 100, 110,
we get an Eye-Diagram. This is used to study Jitter, Voltage swing and Transition time.
The above diagram shows perfect one, practical one respectively.

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Communication, Electronics, Images

Harmonics

In Uncategorized on November 22, 2006 at 8:01 am

Legend : Signal

Dark red: Square wave of amplitude 1

Light red : sin wt

Blue: (1/3)sin 3wt Third Harmonic

Green: (1/5)sin 5wt Fifth Harmonic

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Communication, Electronics, Formula

Transmission lines

In Uncategorized on November 16, 2006 at 9:47 am

Transverse Electromagnetic Waves: Propagation of energy in a transmission line takes place such that electric and magnetic fields transverse to one another and also to direction of propagation. The resultant wave is termed as TEM wave.

Consider a small section n of a parallel wire.

Length of this line is dx.

Voltage at input is V, at the other end is V+dV; Similarly current is I, I+dI.

Assume Primary Line Constants of the line are R,L,G and C

Note: w= 2.pi.f

For small dx, dI is zero.

Potential drop across the line is V – (V+dV) = R.dx.I + jwL.dx.I

à -V’ = I(R+jwL) ….. eq.1

Note: V’ = (d/dx)V

In a similar method, assuming dV is zero,

à -I’ = V(G+iwC) ….. eq.2

Differentiate eq.1,2

V”= V(R+jwL)(G+jwC) ….. eq.3

I” = I(R+jwL)(G+jwC) …..eq.4

Let (gamma)^2 = (R+jwL)(G+jwC)

Gamma = (alpha) + j(beta)

alpha is attenuation constant

beta is phase constant

gamma is propagation constant

Now eq.3,4 becomes

V” = V. (gamma)^2

I” = I. (gamma)^2

Solving the above equations,

V=A.exp(-gamma.x) + B.exp(gamma.x) …..eq.5

I= C.exp(-gamma.x) + D.exp(gamma.x) …..eq.6

Note: exp(x) = e^x

The first terms in eq.5,6 are called incident component(magnitude of V or I decreases from source towards load, whereas the second terms are called reflected component(magnitude of V or I decreases form load towards source)

Hypothetical infinite line: Voltage at distant end approaches zero(i.e no reflected component)

At x=0, V=Vs

Substitute in eq.5, Vs=A+B

At x=infinity, V=0

à B=0, V= Vs.exp(-gamma.x)

V’=-gamma.Vs.exp(-gamma.x)=-(R+jwL)I

Simplifying,

I=(Vs.exp(-gamma.x))/Z0

Where Z0=[(R+jwL)/(G+jwC)]^(1/2)

Z0 the input impedance of such infinite line is commonly referred to as Characteristic Impedance of the line. Z0 and propagation constant are termed as secondary constants (or coefficients) of the line

Line Terminated in a Load Impedance Zr:

At a distance x from the source, voltage and current are Vx, Ix.

-V’=(R+jwL).Ix

Substitute the above after differentiating eq.5,6 and then simplifying,

Voltage, current at source are Vs=A+B, Is=(A-B)/Z0

Vx=Vs.cosh(gamma.x)-Is.Z0.sinh(gamma.x) …..eq.7

Ix=Is.cosh(gamma.x)-(Vs/Z0)sinh(gamma.x) …..eq.8

For load impedance Zr, length of transmission line is l.

Ix=Ir, Vx=Vr such that Vr=Ir.Zr

Substitute the above in eq.7,8, and solve for Vs/Is

Input Impedance Zin = Vs/Is = Z0.N/D

Where N = Zr.cosh(gamma.l) + Z0.sinh(gamma.l)

D= Z0.cosh(gamma.l) + Zr.sinh(gamma.l)

Line Terminated in Load Impedance Z0:

Zr=Z0 in N,D

à Zin=Z0

A line terminated in its characteristic impedance has input impedance equal to Z0. In such a line, there is no reflected component and at any point x distant from the signal source, the voltage and current are same as that for infinite length transmission line.

Low frequency transmission line:

R is very bigger than wL

G is very lesser than wC

Z0 = (R/jwC)^(1/2)

High frequency line:

R is very lesser than wL

G is very lesser than wC

Z0 = (L/C)^(1/2)

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Communication, Electronics

Differential/Balanced transmission

In Uncategorized on November 16, 2006 at 9:45 am

A pair of signal lines(true and inverted) is essential for each channel (there is additional ground return path). Noise is coupled to both wires of the pair, hence rejected by common mode rejection capability of differential amplifier.

Ground noise is also rejected by common mode rejection capability.

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Communication, Electronics

Single-ended transmission

In Uncategorized on November 16, 2006 at 9:42 am

Single-ended transmission is performed on one signal line, and the logical state is interpreted with respect to ground. Twisted pair cable recommended for distance more than 1 metre. E.g. EIA232

The poor noise immunity limits the distance and speed of reliable operation.

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Communication, Electronics

Voltage levels for various bus standards

In Uncategorized on November 16, 2006 at 9:37 am

Single Ended Signals

Standard	VCC	VOH	VIH	Vt	VIL	VOL
5V CMOS	4.5-5.5	VCC-0.2	0.7 VCC	2.5	0.3 VCC	0.5
2.5V CMOS	2.3-2.7	VCC-0.2	0.7 VCC	1.25	0.2 VCC	0.2
3.3V CMOS LVTTL	3.0-3.6	2.4	2.0	1.5	0.8	0.4
5V TTL	4.5-5.5	2.4	2.0	1.5	0.8	0.4
ETL	4.5-5.5	2.4	1.6	1.5	1.4	0.6
GTL		1.2	0.85	0.8	0.75	0.4
GTLP		1.5	1.05	1	0.95	0.55
TIA/EIA-232-F RS-232		5	3	0	-3	-5

Differential Signals

Standard	VDD	VOH	VIH	Vdiff	VIL	VOL
SSTL_3 Class I	3.3	2.1	1.9	0.4	1.1	0.9
SSTL-3 Class II	3.3	2.3	1.9	0.4	1.1	0.7
SSTL_2 Class I	2.5	1.82	1.7	0.35	0.8	0.68
SSTL_2 Class II	2.5	2.01	1.7	0.35	0.8	0.49
USB	4.5-5.5 3.0-3.6		2.0	0.2	1.3
T1A/E1A -644 RS-644 LVDS	2.4	1.32	1.25	Vt=1.2	1.15	1.07

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Communication, Electronics, Formula

Calculation of Characteristic Impedance for given IO standard

In Uncategorized on November 16, 2006 at 9:36 am

Consider 3.3V CMOS, that provides drive capability of 24mA

Max value of VCC is 3.6V.

VOH is 2.4V.

Maximum allowed drop in the transmission line for proper operation is

VCCmax – VOH = 1.2V.

à Maximum allowed impedance of the line is 1.2/0.024 = 50 ohms

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Communication, Electronics

Data Transmission Topologies

In Uncategorized on November 16, 2006 at 9:35 am

Point-to-point: One transmitter, one receiver per line

Multi-drop: One transmitter, many receivers per line

Multi-point: Many transceivers per line

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Communication, Electronics, PCB design

VME protocol

In Uncategorized on November 16, 2006 at 9:33 am

The master puts address onto the bus, delays a minimum of 35ns, and then asserts address strobe. All slave cards on the bus monitor the addresses. Each slave is set up to decode a unique address. For a write operation, the master asserts one or both of its data strobes. The assertion of data strobe tells the slave that data is valid on the bus and can be strobed into memory. The slave then asserts data acknowledge to signal that the data has been captured.

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Electronics, Formula, Memory

SDRAM Calculation of capacity

In Uncategorized on November 16, 2006 at 9:32 am

Calculate the number of addressable locations (don’t think of bit/byte/word for now)

Number of address lines: 11 (A0-A10)

Number of banks : 2 (BA0-BA1)

Max number of rows = 11 (i.e., no. of address lines)

Max number of columns = 11 (i.e., no. of address lines)

Total locations in a bank = 2¹¹x 2¹¹

Total locations in the chip = (No. of banks) x (Total locations in a bank)

= 2² x 2¹¹x 2¹¹

= 2²⁴

Organization: x4, x8, x16

Look for the min possible organization, i.e. x4

Max capacity of the chip is 2²⁴ x4 = 2²⁶bits

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Electronics, Formula, PCB design

Characteristic Impedance of Micro-strip line

In Uncategorized on November 16, 2006 at 9:31 am

Z0=[L/C]^(1/2)= 377(h/w)[Er^{-1/2)]

Er=Relative permittivity of the dielectric material

h = thickness of dielectric

w = trace width

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Electronics

Little Endian vs Big Endian

In Uncategorized on November 7, 2006 at 3:47 am

Little Endian: Little End first; Least significant byte has lowest
address.
Eg. Intel processors

Big Endian: Big End first; Most significant byte has lowest address.
Big Endian byte order is also called network order
Eg. Motorola(Freescale) processors, IBM 370 family, Power PC
architecturesLittle Endian: Little End first; Least significant byte has lowest
address.
Eg. Intel processors

Big Endian: Big End first; Most significant byte has lowest address.
Big Endian byte order is also called network order
Eg. Motorola(Freescale) processors, IBM 370 family, Power PC
architectures

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Electronics

MB vs MiB

In Uncategorized on November 7, 2006 at 3:46 am

MB: Mega Byte
1 MB = 1,000,000 bytes

MiB: Mega bInary Byte ( MeBiByte)
1 MiB = 2^20 Bytes = 1,048,576 bytesMB: Mega Byte
1 MB = 1,000,000 bytes

MiB: Mega bInary Byte ( MeBiByte)
1 MiB = 2^20 Bytes = 1,048,576 bytes

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Electronics, Formula, PCB design

Thumb rule to calculate via inductance

In Uncategorized on November 7, 2006 at 3:46 am

L=5.08h[ln{4h/d)+1] Unit: nH
ln –> natural logarithm
h — > via length (PCB thickness) Unit: inch
d — > via diameter in inches Unit: inchL=5.08h[ln{4h/d)+1] Unit: nH
ln –> natural logarithm
h — > via length (PCB thickness) Unit: inch
d — > via diameter in inches Unit: inch

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Electronics

Edge of digital signal

In Uncategorized on November 7, 2006 at 3:45 am

Trailing : HIGH to LOW
Leading: LOW to HIGH

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audio, Communication, Electronics, i2s, philips, serial

I2S bus

In Bookmarks on November 7, 2006 at 3:44 am

I2S = Inter IC Sound

*Serial bus designed for digital audio devices
*Developed by Philips
*Typical clock 2.5 MHz, Maximum clock speed 3.125 MHz

Signals

SCK: Continuous Serial Clock

WS : Word Select

SD : Serial Data

Device generating SCK, WS is the master

TTL logic levels

VOL < 0.4V

VOH > 2.4V

VIL = 0.8V

VIH = 2.0V

IIL = -15mA

IIH = 0.04mA

Operation: Serial data is transmitted in two’s complement with the MSB first (one clock period after the WS changes).Transmitter and Receiver may have different word lengths(Word length adjustable upto 28 bits).If receiver is sent more bits than its word length, bits after its LSB are ignored. If receiver is sent fewer bits than its word length, missing bits are set to zero internally.Transmitter essentially consists a parallel to serial shift register.SCK defines the data rate. SD is the serial data out from the shift register.WS: The number of clock cycles it is asserted, defines the transmitter word length.Receiver essentially consists a serial to parallel converter.A counter is used at the receiver to count the number of cycles WS is assertedto find the transmitted word length.

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Electronics, PCB design

Reflections on a transmission line

In Uncategorized on November 7, 2006 at 3:43 am

On a long straight line, waves can travel in both directions. Consider a
mechanical transmission line suspended vertically and hung from the
ceiling. Reflections is seen by setting off a pulse from the bottom of
the line. After a time equal to twice the transit time, the pulse
reflects from the ceiling and returns to your hand. This takes a few
seconds. The pulse has been reflected at the top because the line is
anchored there at zero displacement for all time. In an electronic
transmission line, this is equivalent to holding the voltage at zero for
all time by using a short circuit across the line. If you look at the
direction of displacement in the pulse, it reverses on reflection. Thus,
a wave of displacement to the right is returned as a wave of
displacement to the left. In an electronic transmission line, a square
pulse of 1 volt amplitude is returned as a square pulse of -1 volt
amplitude.

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Electronics, Formula, Memory

SDRAM page size

In Uncategorized on November 7, 2006 at 3:42 am

Page size refers to the minimum number of column locations that are on any row and
are accessed with a single ACTIVATE command. This is equal to the number of column
locations times the number of DQ on the device.

Page size = (2^col)*bus_width
where,
col = number of column address lines
bus_width = number of data(DQ) lines

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, DIMM, DIP, DRAM, EEPROM, Electronics, EPROM, Firmware, Flash, Memory, MROM, NAND, NOR, NVRAM, PROM, RAM, ROM, SIMM, SIP, SRAM

Memory Types

In Bookmarks on October 9, 2006 at 9:56 am

Primary Memory Types
Most of the system’s primary memory is located on the system board.
Primary memory typically exists in two or three forms on the system board:

Read-only memory (ROM) contains the computer’s permanent startup programs. ROM devices store information in a permanent fashion and are used to hold programs and data that do not change.

Random access memory (RAM)is quick enough to operate directly with the microprocessor and can be read from, and written to, as often as desired. RAM devices retain the information stored in them only as long as electrical power is applied to the IC. Any interruption of power causes the memory contents to vanish.

Cache memory is a fast RAM system designed to hold data recently accessed from the disk drive that the microprocessor may need again.

ROM
ROM (read-only) memory generally holds data that was programmed into it at the factory, and is not intended to be changed. There are several types of ROM, some of which can be erased and reprogrammed (but not during the normal operation of the computer).

Types of ROM
– Mask-Programmed ROM (MROM) — programmed at the factory.

- Programmable ROM (PROM) — can be custom-programmed by the user (once) using special circuitry.

- Erasable-Programmable ROM (EPROM) — can also be programmed and erased by the user using ultraviolet light and special circuitry external to the computer.

- Electrically Erasable PROM (EEPROM) — can be erased and reprogrammed by special circuitry within the computer.

Non-Volatile Memory
The one thing all forms of ROM have in common is that they are all non-volatile. This means that the data contained in the memory is not lost when the computer is turned off or when electrical power is lost. This enables the computer to begin reading instructions and data from this type of memory as soon as it is powered up.

Read-Only
The term “Read-Only” truly applies to MROM and PROM memories, which are written once and then cannot be erased or rewritten. The other ROM classes are more appropriately referred to as Read Mostly Memories, where the ratio of Read operations to Write operations is very high. The generic term “Read-Only” is used with all non-volatile, semiconductor memories that cannot be written to during the normal operation of the computer.

ROM ICs
Every system board contains one or two ROM ICs that hold the system’s Basic Input/Output System, or BIOS program. The BIOS program contains the basic instructions for communications between the microprocessor and the various input and output devices in the system.

Firmware
The information in the BIOS represents all the intelligence that the computer has until it can load more information from another source, such as a hard or floppy disk. The situation in which programs (software) are stored in ROM chips (hardware) on a permanent basis is referred to as firmware. ROM chips can be located anywhere on the system board, but they are usually easy to recognize due to their relatively large size and immediate proximity to one another.

Flash ROM
Advancements in EEPROM technology have produced Flash ROM devices that enable new BIOS information to be written (downloaded) into the ROM to update it. The download can come from an update disk or another computer.

Flash ROM Information
Unlike RAM ICs, the contents of the Flash ROM remain after the power has been removed from the chip.

NAND Flash vs NOR Flash

Random Access Memory
The other type of high-speed semiconductor memory used with computers and peripheral devices is IC random access memory or RAM. The term “random access” means that any address location in the memory can be accessed as quickly as any other location.

Read/Write Memories
Because there are other types of RAM memory, IC devices used for primary memory are more appropriately referred to as Read/Write (R/W) memories. In the case of primary memory, the generic term “RAM” always refers to semiconductor R/W memory.

Working with Microprocessors
Semiconductor RAM memories are fast enough to work directly with the microprocessor without slowing it down. The computer uses the RAM portion of primary memory to hold programs and data currently being executed by the microprocessor.

RAM Addresses
During the execution of a program, the contents of many RAM address locations are changed as the microprocessor updates the program, by storing intermediate or final results of operations performed.

Types of RAM
Like semiconductor ROM, semiconductor RAM has more than one type. As a matter of fact, it has two general categories: Static RAM (SRAM) Dynamic RAM (DRAM) Although they both perform the same function, the methods they use are completely different

SRAM
Static RAM (SRAM) stores binary bits in such a manner that the bits remain in RAM as long as power to the chip is not interrupted

DRAM
Dynamic RAM (DRAM), on the other hand, requires that stored data be refreshed, or rewritten, periodically to keep it from fading away. As a matter of fact, each bit in the DRAM must be refreshed at least once every 2 milliseconds or the data dissipates

DRAM vs. SRAM
Although the extra circuitry and inconvenience associated with refreshing may initially make DRAM memory seem the obvious second choice behind SRAM, this is not the case.

The Economical Choice
Due to the simplicity of DRAM’s internal structure, the bit storage capacity of a DRAM chip is much greater than that of a similar SRAM chip. The DRAM chip also offers a much lower rate of power consumption. Both of these factors contribute to making DRAM memory the economical choice in certain RAM memory systems.

Using SRAM or DRAM
Generally, SRAM is used in smaller memory systems where the added cost of refresh circuitry would greatly add to the cost per bit of storage. DRAM is used in larger memory systems where the extra cost of refresh circuitry is distributed over a greater number of bits and is offset by the reduced operating cost associated with DRAM chips.

Volatile Memory
Both SRAM and DRAM have the disadvantage of being volatile. This means that any data stored in RAM is lost if power to the computer is disrupted for any reason. On the other hand, both types of RAM have the advantage of being fast: They can be written into and read from with equal ease.

DIP
In earlier PC designs — XT and AT — the system’s RAM memory was comprised of banks of discrete RAM ICs in Dual In-line Pin (DIP) sockets.

SIP
Intermediate clone designs placed groups of RAM ICs on small 30-pin daughterboards that plugged into the system board vertically. This mounting method required less horizontal board space. These RAM modules had pins along one side of the board and were referred to as single in-line pin (SIP) modules.

SIMMs and DIMMs
Further refinements of the RAM module produced snap-in, single in-line memory modules (SIMMs), and dual in-line memory modules (DIMMs). SIMM and DIMM units mount vertically on the system board. However, rather than using a pin and socket arrangement, both use special snap-in sockets that support the module firmly.

SIMM and DIMM Qualities
SIMMs and DIMMs are also keyed, so that they cannot be plugged in backwards.
SIMMs are available in 30- and 72-pin versions; DIMMs are larger 168-pin boards.

Memory Modules
PCs are usually sold with less than their full RAM capacity. This enables a user to purchase a less expensive computer to fit the user’s individual needs, and yet retain the option to install more RAM if future applications call for it.

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Communication, Electronics, PCB design

Relative Dielectric Constants

In Uncategorized on October 9, 2006 at 9:53 am

Material	Er
Air	1.0
PTFE/glass 2800	2.2
Rogers RO	2.9
CE/goreply	3.0
BT/goreply	3.3
GETEK	3.5
CE/glass	3.7
Silicon dioxide	3.9
BT/glass	4.0
Polymide/glass	4.1
FR-4/glass	4.1
Glass cloth	6.0
Alumina	9.0

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Electronics, Formula

Reset Scheme

In Uncategorized on January 17, 2006 at 10:04 am

Given Data:

50 ms <=RC

Let C=10uF

0.05 = R/100000

R= 5k

Available

R=4.7k

C= 11uF (10uF + 1uF)

Time constant= 51.7 ms

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