Friis transmission equation

Path loss = 20 log (4 * pi * r / lambda)

[Note: use log base 10]

where,

Path loss = signal attenuation. Unit: dB

pi = 22 / 7

r = distance between transmitter and receiver. Unit: m

lambda = wavelength of signal. Unit: m

Wavelength = C/f

where,

C = speed of electromagnetic waves in free space

= 299792458. Unit: m / s

f = frequency of signal. Unit: Hz

Let r = R * (2 ^ x)

Path loss = 20 log (4 * pi * R * L / lambda)

= 20 log (4 * pi * R / lambda) + 20 log (2 ^ x)

= 20 log (4 * pi * R / lambda) + 6x

The above derivation implies range(R) doubles every 6dB of path loss.

The path loss is +8.519dB more over a given range for the 2.4 GHz compared to 900MHz for the same range. In other words operating at 900 MHz exhibits a significantly longer range than is possible at 2.4 GHz.

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High speed digital buses

Bus	Clock Frequency
RapidIO	1 GHz
Hypertransport	800 MHz
3GIO	1.25 GHz
Serial ATA	3 GHz
SCID	1.6 GHz
Infiniband	1.25 GHz
Gigabit Ethernet	625 MHz

USB – Universal Serial Bus

USB is a polled cable bus with single-host-scheduled, token-based protocol.

Tiered-star topology: USB host is the root hub. A hub is center of a star. A star consists of point-to-point connections between [host and hub/function] or [hub and (another) hub/function].

Allowed topology: Maximum tiers = 7; Maximum non-root hubs in a tier = 5.

Data rates:

High-speed: 480 Mbps

Full-speed: 12 Mbps

Low-speed: 1.5Mbps

For effective utilization of bandwidth, full-speed and low-speed data can be transmitted at high-speed between host and hub, but transmitted between hub and device at full-speed or low-speed.

Operation: Clock is transmitted, encoded (NRZI encoding with bit stuffing) with differential data. A SYNC field precedes each packet for synchronization. The cable also carries VBUS (+5V at source) and GND to deliver power to devices. Cable with biased terminations at each end and up to seven metre length is allowed.

Most bus transactions involve the transmission of up to three packets. Each transaction begins when the Host Controller, on a scheduled basis, sends a USB packet describing the type and direction of transaction, the USB device address, and endpoint number. This packet is referred to as the “token packet.” The USB device that is addressed selects itself by decoding the appropriate address fields. In a given transaction, data is transferred either from the host to a device or from a device to the host. The direction of data transfer is specified in the token packet. The source of the transaction then sends a data packet or indicates it has no data to transfer. The destination, in general, responds with a handshake packet indicating whether the transfer was successful.

Some bus transactions between host controllers and hubs involve the transmission of four packets. These types of transactions are used to manage the data transfers between the host and full-/low- speed devices. The USB data transfer model between a source or destination on the host and an endpoint on a device is referred to as a pipe. There are two types of pipes: stream and message. Stream data has no USB-defined structure, while message data does. Additionally, pipes have associations of data bandwidth, transfer service type, and endpoint characteristics like directionality and buffer sizes. Most pipes come into existence when a USB device is configured. One message pipe, the Default Control Pipe, always exists once a device is powered, in order to provide access to the device’s configuration, status, and control information.

The transaction schedule allows flow control for some stream pipes. At the hardware level, this prevents buffers from under-run or overrun situations by using a NAK handshake to throttle the data rate. When NAKed, a transaction is retried when bus time is available. The flow control mechanism permits the construction of flexible schedules that accommodate concurrent servicing of a heterogeneous mix of stream pipes. Thus, multiple stream pipes can be serviced at different intervals and with packets of different sizes.

UART

Universal Asynchronous Receiver Transmitter: Used for serial communications via cable.  UART generates signals of same timing as RS-232 used by Personal Computer’s COM ports. 

Standard	Logic 0	Logic 1
UART	0V	5V
RS-232	+12V	-12V

 
Asynchronous communication requires clock recovery, where a known transition event in the data is used to synchronize transmitter/receiver.

Baud rate of UART: integer multiples or submultiples of 9600 Hz.

RS-232 frame:

1) Start bit (always logic 0)

2) Data bits (5, 6, 7, or 8 of them)

3) A parity bit (optional, even or odd parity)

4) A stop bit (always logic 1); may be 1, 1.5, 2 bit times in duration

 
The synchronization point is at the start of the frame (always a 1 to 0 transition).

• The 8 received data values are sampled 1.5BT, 2.5BT, … , 8.5BT after the synchronization point (BT = bit time).

• The stop bit is sampled 9.5BT after the synchronization point (if it is not a logic 1, this is a framing error).

Send, Receive data are buffered using Tx, Rx registers.

JTAG

JTAG: Joint Test Action Group

Boundary Scan technology has the ability to set and read values on pins without direct physical access. Boundary Scan Register: Intercepts device’s core logic and its pins which is invisible for normal operation. In test mode these cells can be used to set/read values.

TCK: Test ClocK synchronizes the internal state machine operations

TMS: Test Mode State’ is sampled at the rising edge of TCK to determine the next state.

TDI: Test Data In represents the data shifted into the device’s test or programming logic. It is sampled at the rising edge of TCK when the internal state machine is in the correct state.

TDO: Test Data Out represents the data shifted out of the device’s test or programming logic and is valid on the falling edge of TCK when the internal state machine is in the correct state.

TRST: Test Reset is an optional pin which, when available, can reset the TAP controller’s state machine.

Instruction Register: Defines to which of the data registers signals should be passed.

Data Registers:

BSR- Boundary Scan Register: The main testing data register used to move data to and from the ‘pins’ on a device.

BYPASS Register: A single-bit register that passes information from TDI to TDO.

IDCODES Register: Contains the ID code and revision number for the device. This information allows the device to be linked to its Boundary Scan Description Language (BSDL) file.

The IEEE 1149.1 standard defines a set of instructions that must be available for a device to be considered compliant.

TAP (Test Access Port) controller: A state machine whose transitions are controlled by TMS signal. All states have two exits (for TMS=0, TMS=1). Two main paths (in the state machine) allow for setting or retrieving information from either a data register or the instruction register on the device. The data register operated on (e.g. BSR, IDCODES, BYPASS) depends on the value loaded into the instruction register.

PCI Express

One PCIe lane consists of a differential Tx pair, Rx pair. One PCIe link consists at-least one lane. An xN link denotes N lanes. Supported link widths: x1, x2, x4, x8, x16, x32.

Raw Bandwidth: 2.5Gbps/lane/direction.

During hardware initialization, each PCI Express Link is set up following a negotiation of Lane widths and frequency of operation by the two agents at each end of the Link. No firmware or operating system software is involved.

A PCIe fabric consists of point-to-point links that interconnect a set of components. Root complex at the top of the hierarchy connects CPU/memory subsystem to the I/O (End-point device, switch, PCIe-PCI bridge, etc). Each of the components is mapped in a single flat address space and can be accessed using PCI-like load/store accesses transaction semantics.

Load-store mechanism in PCI: From the CPU’s perspective, PCI devices are accessible via a fairly straightforward load-store mechanism. There’s flat, unified chunk of address space dedicated for PCI use, which looks to the CPU much like a flat chunk of main memory address space, the primary difference being that at each range of addresses there sits a PCI device instead of a group of memory cells containing code or data. When a PCI-enabled computer boots up, it must initialize the PCI subsystem by assigning chunks of the PCI address space to the different devices so that they’ll be accessible to the CPU.

PCI Express’s designers have left this load-store-based, flat memory model unchanged. So a legacy application that wants to communicate via PCIe still executes a read from or a write to a specific address. Hence PCIe is backwards-compatible with PCI, and that operating systems can boot on and use a PCIe-based system without modification.

Note: In PCI system, devices are connected to host (root) through a shared bus (parallel bus). There is an arbitration scheme that decides who gets access to the bus. In PCIe system, devices are connected to root complex by point-to-point connection (serial connection).

PCI Express uses packets to communicate information between components. The capability to route peer-to-peer transactions between hierarchy domains through a Root Complex is optional and implementation dependent. For example, an implementation may incorporate a real or virtual Switch internally within the Root Complex to enable full peer-to-peer support in a software transparent way.

1U

U is unit of measure for vertical usable space, or height of racks, cabinets. 1U is equal to 1.75 inches (44.45mm).

Example : Form-factor of 3U cPCI board is 100mm x 160mm

Form-factor of 6U cPCI board is 100mm x 233.35mm

Note: 3U as per the definition is 3 x 44.45 mm = 133.35. But 160mm is defined in the cPCI specifications.

PCI – Peripheral Component Interconnect

 

All signals except Reset, Interrupt are sampled at rising edge of clock.

Operation:
A bus transaction is followed by an address phase followed by one or more data phases. Address phase starts when FRAME# is asserted. For read operation TRDY#(target ready) is asserted. For write operation IRDY#(initiator ready) is asserted. Data phase completes on any clock both IRDY#, TRDY# are asserted. Wait cycles are inserted until both are asserted together.

Address, Data pins are multiplexed. C/BE# pins are multiplexed. They define bus command for address phase, byte enable for data phase. STOP# signal indicates the current target is requesting the master to stop the current transaction. LOCK# used for atomic operations. IDSEL (Initialization Device select) used as chip select for configuration read, write transactions. DEVSEL# indicates whether any device on the bus is selected. Arbitration signals (REQ#, GNT#) of bus master: request, grant access to bus provided RST# is de-asserted.

PAR – even parity signal; has same timing of address/data but delayed by one clock. PAR is driven by master for address, write data phases, and by slave for read data phases. PERR#, SERR# report data parity error, system error(address/command) respectively. M66EN indicates 33MHz or 66MHz. ACK64# acknowledges 64 bit transfer.

Optional Signals:
INTA#, INTB#, INTC#, INTD# — request interrupt. PRSNT indicates the motherboard presence of add-in board. CLKRUN# indicates status of CLK. PME — asynchronous signal used to request a change is system power state. 3.3VAUX — auxiliary power source. TCK, TDI, TDO, TMS, TRST# — JTAG signals

OSI Reference Model – Easy way to remember

 

 

Application Layer: End user processes like file transfer, e-mail, network software services. E.g. Telnet, FTP

 

Presentation/Syntax Layer: Format, Encrypt data to send across network.

 

Session Layer: Establishes, manages and terminates connections between applications .

 

Transport Layer: End-to-end error recovery, flow control.

 

Network Layer: Switching, Routing, Addressing, internetworking, error handling, congestion control and packet sequencing.

 

Data Link Layer: Encoding, decoding data packets into bits.

Media Access Control Sub-layer: Data access/transmit permissions.

Logical Link Sub-layer: Frame synchronization, flow control, error checking.

 

Physical Layer: Conveys the bit stream (electrical, light, radio)

E.g. Ethernet, RS232, ATM

 

An easy way to remember : use the following quotes

“All People Seem To Need Data Processing”

“People Do Not Trust Sales People Always”

SPI interface

 

 

The SPI-bus is a 4-wire serial communications interface used by many microprocessor peripheral chips. The Serial Peripheral Interface (SPI) circuit is a synchronous serial data link that is standard across many Motorola microprocessors and other peripheral chips. It provides support for a low/medium bandwidth (1 megabaud) network connection amongst CPUs and other devices supporting the SPI.

SPI bus is basically a relatively simple synchronous serial interface for connecting low speed external devices using quite minimal number of wires. SPI (serial peripheral interface) is an interface standard defined by Motorola on the MC68HCxx line of microcontrollers. A synchronous clock shifts serial data into and out of the microcontrollers in blocks of 8 bits. SPI – Serial Peripheral Interface. SPI is used frequently in handheld and other mobile platform systems.

SPI bus is a master/slave interface. Whenever two devices communicate, one is referred to as the “master” and the other as the “slave” device. The master drives the serial clock. When using SPI, data is simultaneously transmitted and received, making it a full-duplexed protocol.

Motorola’s names for the signals are as follows: SCLK for serial clock, which is always driven by the master: MISO is master-in slave-out data: MOSI is master-out slave-in data. In a typical application, connect the microcontroller’s SCLK to the converter’s SCLK input, connect the MISO to the converter’s DOUT pin, and connect the MOSI pin to the converter’s DIN pin. Serial protocols such as SPI, a chip-select input is required to enable the IC. Using this chip-select signal it is possible to connect many ICs to same SPI bus in parallel. If there is a chip-select (CS) signal in use, it can be driven by a spare microcontroller general-purpose output. Every IC connected to bus needs it’s own chip-select signal line. Thus, when 10 devices are on the bus, 10 chip-select lines, in addition to the shared clock and data lines, are needed to select the appropriate device.

 

 

The SPI interface is based on a 8 bit shift register. The shift clock (SCK) is provided by the master device. SCK is a gated clock and is only generated during shifting. SCK stays idle between transfers. Transmitting and receiving occurs simultaneously: While the master shifts out it’s transmit data, data from the slave is shifted in. As a result, the master must always send data in order to generate clocks, even if only data reception is required. The following diagram shows a basic interface and a sample data transfer: Data on SDO is shifted out with the falling SCK edge; data on SDI is sampled on the rising SCK edge. The SCK idle polarity is ‘High’.

Eye Diagram

By super-imposing the transition patterns of a signal for 011, 001, 100, 110,
we get an Eye-Diagram. This is used to study Jitter, Voltage swing and Transition time.
The above diagram shows perfect one, practical one respectively.

Harmonics

Legend : Signal

Dark red: Square wave of amplitude 1

Light red : sin wt

Blue: (1/3)sin 3wt Third Harmonic

Green: (1/5)sin 5wt Fifth Harmonic

Transmission lines

Transverse Electromagnetic Waves: Propagation of energy in a transmission line takes place such that electric and magnetic fields transverse to one another and also to direction of propagation. The resultant wave is termed as TEM wave.

Consider a small section n of a parallel wire.

Length of this line is dx.

Voltage at input is V, at the other end is V+dV; Similarly current is I, I+dI.

Assume Primary Line Constants of the line are R,L,G and C

Note: w= 2.pi.f

For small dx, dI is zero.

Potential drop across the line is V – (V+dV) = R.dx.I + jwL.dx.I

à -V’ = I(R+jwL) ….. eq.1

Note: V’ = (d/dx)V

In a similar method, assuming dV is zero,

à -I’ = V(G+iwC) ….. eq.2

Differentiate eq.1,2

V”= V(R+jwL)(G+jwC) ….. eq.3

I” = I(R+jwL)(G+jwC) …..eq.4

Let (gamma)^2 = (R+jwL)(G+jwC)

Gamma = (alpha) + j(beta)

alpha is attenuation constant

beta is phase constant

gamma is propagation constant

Now eq.3,4 becomes

V” = V. (gamma)^2

I” = I. (gamma)^2

Solving the above equations,

V=A.exp(-gamma.x) + B.exp(gamma.x) …..eq.5

I= C.exp(-gamma.x) + D.exp(gamma.x) …..eq.6

Note: exp(x) = e^x

The first terms in eq.5,6 are called incident component(magnitude of V or I decreases from source towards load, whereas the second terms are called reflected component(magnitude of V or I decreases form load towards source)

Hypothetical infinite line: Voltage at distant end approaches zero(i.e no reflected component)

At x=0, V=Vs

Substitute in eq.5, Vs=A+B

At x=infinity, V=0

à B=0, V= Vs.exp(-gamma.x)

V’=-gamma.Vs.exp(-gamma.x)=-(R+jwL)I

Simplifying,

I=(Vs.exp(-gamma.x))/Z0

Where Z0=[(R+jwL)/(G+jwC)]^(1/2)

Z0 the input impedance of such infinite line is commonly referred to as Characteristic Impedance of the line. Z0 and propagation constant are termed as secondary constants (or coefficients) of the line

Line Terminated in a Load Impedance Zr:

At a distance x from the source, voltage and current are Vx, Ix.

-V’=(R+jwL).Ix

Substitute the above after differentiating eq.5,6 and then simplifying,

Voltage, current at source are Vs=A+B, Is=(A-B)/Z0

Vx=Vs.cosh(gamma.x)-Is.Z0.sinh(gamma.x) …..eq.7

Ix=Is.cosh(gamma.x)-(Vs/Z0)sinh(gamma.x) …..eq.8

For load impedance Zr, length of transmission line is l.

Ix=Ir, Vx=Vr such that Vr=Ir.Zr

Substitute the above in eq.7,8, and solve for Vs/Is

Input Impedance Zin = Vs/Is = Z0.N/D

Where N = Zr.cosh(gamma.l) + Z0.sinh(gamma.l)

D= Z0.cosh(gamma.l) + Zr.sinh(gamma.l)

Line Terminated in Load Impedance Z0:

Zr=Z0 in N,D

à Zin=Z0

A line terminated in its characteristic impedance has input impedance equal to Z0. In such a line, there is no reflected component and at any point x distant from the signal source, the voltage and current are same as that for infinite length transmission line.

Low frequency transmission line:

R is very bigger than wL

G is very lesser than wC

Z0 = (R/jwC)^(1/2)

High frequency line:

R is very lesser than wL

G is very lesser than wC

Z0 = (L/C)^(1/2)

Differential/Balanced transmission

A pair of signal lines(true and inverted) is essential for each channel (there is additional ground return path). Noise is coupled to both wires of the pair, hence rejected by common mode rejection capability of differential amplifier.

Ground noise is also rejected by common mode rejection capability.

Single-ended transmission

Single-ended transmission is performed on one signal line, and the logical state is interpreted with respect to ground. Twisted pair cable recommended for distance more than 1 metre.  E.g. EIA232

The poor noise immunity limits the distance and speed of reliable operation.

 

Voltage levels for various bus standards

Single Ended Signals

Standard	VCC	VOH	VIH	Vt	VIL	VOL
5V CMOS	4.5-5.5	VCC-0.2	0.7 VCC	2.5	0.3 VCC	0.5
2.5V CMOS	2.3-2.7	VCC-0.2	0.7 VCC	1.25	0.2 VCC	0.2
3.3V CMOS LVTTL	3.0-3.6	2.4	2.0	1.5	0.8	0.4
5V TTL	4.5-5.5	2.4	2.0	1.5	0.8	0.4
ETL	4.5-5.5	2.4	1.6	1.5	1.4	0.6
GTL		1.2	0.85	0.8	0.75	0.4
GTLP		1.5	1.05	1	0.95	0.55
TIA/EIA-232-F RS-232		5	3	0	-3	-5

Differential Signals

Standard	VDD	VOH	VIH	Vdiff	VIL	VOL
SSTL_3 Class I	3.3	2.1	1.9	0.4	1.1	0.9
SSTL-3 Class II	3.3	2.3	1.9	0.4	1.1	0.7
SSTL_2 Class I	2.5	1.82	1.7	0.35	0.8	0.68
SSTL_2 Class II	2.5	2.01	1.7	0.35	0.8	0.49
USB	4.5-5.5 3.0-3.6		2.0	0.2	1.3
T1A/E1A -644 RS-644 LVDS	2.4	1.32	1.25	Vt=1.2	1.15	1.07

Calculation of Characteristic Impedance for given IO standard

Consider 3.3V CMOS, that provides drive capability of 24mA

Max value of VCC is 3.6V.

VOH is 2.4V.

Maximum allowed drop in the transmission line for proper operation is

VCCmax – VOH = 1.2V.

à Maximum allowed impedance of the line is 1.2/0.024 = 50 ohms

Data Transmission Topologies

Point-to-point: One transmitter, one receiver per line

Multi-drop: One transmitter, many receivers per line

Multi-point: Many transceivers per line

VME protocol

The master puts address onto the bus, delays a minimum of 35ns, and then asserts address strobe.  All slave cards on the bus monitor the addresses. Each slave is set up to decode a unique address.  For a write operation, the master asserts one or both of its data strobes.  The assertion of data strobe tells the slave that data is valid on the bus and can be strobed into memory. The slave then asserts data acknowledge to signal that the data has been captured.

I2S bus

 

I2S = Inter IC Sound

*Serial bus designed for digital audio devices
*Developed by Philips
*Typical clock 2.5 MHz, Maximum clock speed 3.125 MHz

Signals

SCK: Continuous Serial Clock

WS : Word Select

SD : Serial Data

Device generating SCK, WS is the master

TTL logic levels

VOL < 0.4V

VOH > 2.4V

VIL = 0.8V

VIH = 2.0V

IIL = -15mA

IIH = 0.04mA

Operation: Serial data is transmitted in two’s complement with the MSB first (one clock period after the WS changes).Transmitter and Receiver may have different word lengths(Word length adjustable upto 28 bits).If receiver is sent more bits than its word length, bits after its LSB are ignored. If receiver is sent fewer bits than its word length, missing bits are set to zero internally.Transmitter essentially consists a parallel to serial shift register.SCK defines the data rate. SD is the serial data out from the shift register.WS: The number of clock cycles it is asserted, defines the transmitter word length.Receiver essentially consists a serial to parallel converter.A counter is used at the receiver to count the number of cycles WS is assertedto find the transmitted word length.

Relative Dielectric Constants

Material	Er
Air	1.0
PTFE/glass 2800	2.2
Rogers RO	2.9
CE/goreply	3.0
BT/goreply	3.3
GETEK	3.5
CE/glass	3.7
Silicon dioxide	3.9
BT/glass	4.0
Polymide/glass	4.1
FR-4/glass	4.1
Glass cloth	6.0
Alumina	9.0