Packed Array vs Unpacked Array
Packed array – made of sub-dividing a vector into subfields which can be conveniently accessed as array elements. Also is guaranteed to be represented as a contiguous set of bits. Unpacked array may or many not be so represented.

Usage of arrays
Packed/Unpacked array – Size Known at Compile time
Dynamic array – Size Known at Run-time
Queues – Size Varying at Run-time
Associative array – Index/Key can be random. Sparse Memory Models. Scoreboard for out-of-order transactions

Struct vs. Union
Struct occupies memory of Sum of sizes of all members.
Union occupies memory of Largest sized member. All members point to the same memory location. Tagged Union can declare methods of void type.

Struct vs. Class
Struct can’t have methods. No OOPs ??

Reg vs. Logic
Use logic instead of reg. Intent – deprecate use of reg in future.

Protected vs. Private/Local
Private – Members(fields/methods) can only be accessed within the same scope
Protected – Similar to Private except that Members can be accessed in a derived class

What is polymorphism?
Non-OOP form – Function overloading in C++
OOP form – Dynamic lookup of virtual functions

What is virtual function?
Function which can be over-ridden by extending the class

Use of Packages
Explicit named scope. Similar to namespace in C++
It may contain typedef, variables, functions, sequences and properties

Use of Program Block
Eliminate test-bench race by avoiding non-determinism.
Statements (initial blocks) sensitive to design (module) signals are scheduled in Reactive region.
Initial blocks in modules are scheduled in Active region. Design signals driven from program using non-blocking assignments are updated in NBA region.

Use of Virtual Interface
Separate abstract models from actual signals

Latch

• Asynchronous

• Level Sensitive

• Clock signal = Enable signal* = Latch Signal

o It is not apt to call it Clock; better call it Enable

o When ‘1’, Q changes when D changes

o When ‘0’, Q retains state

• Used as Mechanical Switch De-bouncer

• Processor ALE signal implemented using Latch

Flip Flop

• Edge Sensitive (Master-Slave Flip Flop)

• Clock signal = Enable signal* = Gating Signal

o When ‘1’, Q depends on D; Q doesn’t change till next Clock.

o When ‘0’, Q retains state

• All sequential logic implemented using Flip Flops

I have my airtel broadband connection activated.
Airtel Engineer had done the setup and activation on WindowsXP.
After he left, I did a reboot to openSUSE.

Then I just followed the instructions as given in the below site.
Pasting it without changing a word

=====================================================================
http://kasolutions.wordpress.com/2009/05/14/using-airtel-broadband-in-linux/

yesterday i sweated a lot for bringing up airtel braodband in linux. to save water (!) please read the instructions.
pre-requisites
airtel router ip , subnet mask , supplied IP
generally it is 192.168.1.1
to find out this, use windows. connect to windows and wait for the “LAN in now connected” pop up
open up a command prompt and type in “ipconfig”
from the listing, look for something like this
Ethernet adapter Local Area Connection:Connection-specific DNS Suffix . :IP Address. . . . . . . . . . . . : 192.168.1.36Subnet Mask . . . . . . . . . . . : 255.255.252.0Default Gateway . . . . . . . . . : 192.168.1.15
Ethernet adapter Local Area Connection:
Connection-specific DNS Suffix . :
IP Address. . . . . . . . . . . . : 192.168.1.2 => your machine’s IP (note this down)
Subnet Mask . . . . . . . . . . . : 255.255.255.0 => mask (note this down)
Default Gateway . . . . . . . . . : 192.168.1.1 => airtel router’s IP (note this down)
We are all set to get into linux. Follow the steps in their order
From a shell execute the commands
1. $ ifconfig eth0 192.168.1.2
this sets IP for eth0 . to know which eth link you have, execute the command “ifconfig -a” and look for the link eth
2. $ route add default gw 192.168.1.1
this sets default gateay as airtel router
3. $ vim /etc/resolv.conf
add this line
nameserver 192.168.1.1
to the file’s end after commenting out all the other lines (for commenting, put a “#” at the beginning of a line)
4. $ ping www.google.com
it will work
Thats it. Browse away

=====================================================================

Note: ifconfig, route commands require superuser privileges
Type su, then enter password and do steps 1 through 3
For fourth step, superuser privilege is not required.
Type exit and call the ping command as a normal user

Within a minute I was able to browse from my openSUSE.
That was really nice.

Then I did a restart into openSUSE
Now I was not able to browse anything.
Sadly I had to repeat the above steps again to start with.

Then I looked up the Control Center to see if these settings
could be saved. Couldn’t do it successfully.

Finally I did a try as given below; it worked right away
Computer -> Control Center -> Network Settings
-> Global Options:

• Traditional Method with ifup
• Enable IPv6
• Hostname to send AUTO
• Change Default route via DHCP

-> Overview -> Edit
-> General

• Activate device at boot time

-> Address

• Dynamic Address DHCP

-> Hardware

• Device name eth0

Download here. singleton-design-pattern
C++ example for singleton design pattern: click here

System Verilog example for singleton design pattern

// Filename  : singleton.sv
// Author    : A.G.Raja
// License   : GPL
// Website   : http://agraja.wordpress.com

module tb;

class Singleton;
// object that is created only once
extern static Singleton single;
// constructor that is called only once
extern function new;
// method to get object
extern function Singleton get_instance;
// data to check the functionality
int data;
endclass

initial Singleton::single = null;

function Singleton::new;
data = 14;
endfunction

function Singleton Singleton::get_instance;
// call the constructor for the first time
// if the object has been created already
// return reference to the object already created
if(single==null) single = new;
// return the reference to the object
return single;
endfunction

Singleton s, t;

initial begin
// don’t use s= new;
// since it will create new instances
// instead use the get_instance method
s = s.get_instance();
t = t.get_instance();
$display(“initial value of s.data  = “,s.data);
s.data = 25;
$display(“modified value of s.data = “,s.data);
$display(“value of t.data          = “,t.data);
end
endmodule

Result:
initial value of s->data  = 14
modified value of s->data = 25
value of t->data          = 25
Download here. singleton-design-pattern

Purpose of a singleton:
To have a class which has only one instance(object)
All the objects of this class refer to same global object
that is created only once
This design pattern provides a mechanism for providing
namespaces to global variables

C++ example for singleton design pattern

// Filename  : singleton.cpp
// Author    : A.G.Raja
// License   : GPL
// Website   : http://agraja.wordpress.com

#include <iostream>

using namespace std;

class Singleton {
// constructor that is called only once
Singleton();
// object that is created only once
static Singleton *single;
public:
// method to get object
Singleton* get_instance();
// data to check the functionality
int data;
};

Singleton* Singleton::single = NULL;

Singleton* Singleton::get_instance() {
// call the constructor for the first time
// if the object has been created already
// return reference to the object already created
if(single==NULL) single = new Singleton();
return single;
}

Singleton::Singleton() {
data = 14;
}

int main() {
Singleton *s, *t ;
s = s->get_instance();
cout<<”initial value of s->data  = “<<s->data<<endl;
s->data = 25;
cout<<”modified value of s->data = “<<s->data<<endl;
t = t->get_instance();
cout<<”value of t->data          = “<<t->data<<endl;
}
// end of file singleton.cpp

Result:
initial value of s->data  = 14
modified value of s->data = 25
value of t->data          = 25

Download here.  singleton-design-pattern

// Filename    : virtual_interface.sv
// Author      : A.G.Raja
// License     : GPL
// Website     : http://agraja.wordpress.com

interface bus(input wire clk);
int address;
int data;

modport virtual_interface(input clk);
endinterface

module virtual_interface;
bit clk;
bus BUS(clk);
class monitor;
virtual bus VBUS;
task disp;
$display(VBUS.address);
$display(VBUS.data);
endtask
endclass
monitor m;

initial begin
m = new;
m.VBUS = BUS;
BUS.address = 100;
BUS.data    = 1234;
m.disp;
end
endmodule

// Running simulation in ncverilog
// ncverilog +sv virtual_interface.sv

// Running simulation in modelsim/questasim
// vlib work
// vlog -sv virtual_interface.sv
// vsim -c virtual_interface
// run

Download here. system_verilog_virtual_interface

// Filename    : tlm.sv
// Author      : A.G.Raja
// License     : GPL
// Website     : http://agraja.wordpress.com

module producer_consumer;

virtual class put_if;

// Abstract Class whose methods are not yet implemented
virtual task put(int val);
endtask
endclass

class producer;
put_if put_port;
task run;
int i;
for(i=0;i<10;i++) put_port.put(i);
endtask
endclass

class consumer extends put_if;

// methods of put_if class are over-ridden

// and defined here
task put(int val);
$display(“Consumer receiving “,val);
endtask
endclass

producer p;
consumer c;

initial begin
p = new;
c = new;
p.put_port = c;
p.run;
end
endmodule

// Running simulation in ncverilog

ncverilog +sv tlm.sv

// Running simulation in modelsim/questasim

vlib work

vlog -sv tlm.sv

vsim -c producer_consumer

run

Download here. transactionlevelmodeling_systemverilog

Here is hello world program in

System Verilog Open Verification Methodology

Download here. hello_ovm

// Filename : hello_ovm.sv

// Author : A.G.Raja

// License : GPL

// Website : http://agraja.wordpress.com

module hello_ovm;

`include “ovm.svh”

class Random extends ovm_transaction;

rand int num;

constraint c { num >= 0 && num < 50; }

function new(string name);

super.new(name);

endfunction

endclass

Random r;

initial begin

r = new(“Hello OVM”);

r.print();

ovm_report_message(“APPLIED ELECTRONICS JOURNAL”,

$psprintf(“Hello World”));

end

endmodule

// End of file hello_ovm.sv

One liner to run this in IUS

When OVM library is not installed by default:

1) Set OVMHOME to the root directory where OVM library is installed

setenv OVMHOME /netstar/ag.raja/sv/OVM/ovm-1.1

2.a) IUS 6.2-s003 and IUS 6.2-s004

irun -sv -nowarn PMBDVX -ovmhome $OVMHOME $OVMHOME/src/ovm_pkg.sv hello_ovm.sv

2.b) IUS 6.2-s005

irun -sv -ovmhome $OVMHOME $OVMHOME/src/ovm_pkg.sv hello_ovm.sv

When OVM is already installed to $CDS_INST_DIR/tools/ovm

a) IUS 6.2-s003 and IUS 6.2-s004

irun -sv -ovm -nowarn PMBDVX hello_ovm.sv

b) IUS 6.2-s005

irun -sv -ovm hello_ovm.sv

Using Options File

irun –f options_file

// options_file begins here

-sv

-ovm

hello_ovm.sv

// options_file ends here

Download here. hello_ovm

Create a file named “.vimrc” in your home directory [*nix]

Put the following lines in that file

“File Begins here

“Note: Comments in vim script begin with double quote

“Filename : .vimrc

“Author    :  A.G.Raja

“Website  : http://agraja.wordpress.com

“Show line numbers

set nu

“Source the syntax file

so $VIMRUNTIME/syntax/verilog.vim

“Add file extensions to be highlighted

au Syntax sv runtime! syntax/verilog.vim

au Syntax svh runtime! syntax/verilog.vim

au Syntax vpp runtime! syntax/verilog.vim

au Syntax svpp runtime! syntax/verilog.vim

au Syntax svhpp runtime! syntax/verilog.vim

“End of file

// Filename    : string_wstring.cpp
// Author      : A.G.Raja
// License     : GPL
// Website     : http://agraja.wordpress.com

#include <iostream>

using namespace std;

string wstring2string(wstring wstr) {
string str(wstr.length(),’ ‘);
copy(wstr.begin(),wstr.end(),str.begin());
return str;
}

wstring string2wstring(string str) {
wstring wstr(str.length(),L’ ‘);
copy(str.begin(),str.end(),wstr.begin());
return wstr;
}

int main() {
wstring wstr = string2wstring(“raja”);
string str = wstring2string(wstr);
cout<<str<<endl;
}

Download here. string-wstring-conversion-functions