System Verilog Singleton Example

Purpose of a singleton:
To have a class which has only one instance(object)
All the objects of this class refer to same global object
that is created only once
This design pattern provides a mechanism for providing
namespaces to global variables

Download here. singleton-design-pattern
C++ example for singleton design pattern: click here

System Verilog example for singleton design pattern

// Filename  : singleton.sv
// Author    : A.G.Raja
// License   : GPL
// Website   : http://agraja.wordpress.com

module tb;

class Singleton;
// object that is created only once
extern static Singleton single;
// constructor that is called only once
extern function new;
// method to get object
extern function Singleton get_instance;
// data to check the functionality
int data;
endclass

initial Singleton::single = null;

function Singleton::new;
data = 14;
endfunction

function Singleton Singleton::get_instance;
// call the constructor for the first time
// if the object has been created already
// return reference to the object already created
if(single==null) single = new;
// return the reference to the object
return single;
endfunction

Singleton s, t;

initial begin
// don’t use s= new;
// since it will create new instances
// instead use the get_instance method
s = s.get_instance();
t = t.get_instance();
$display(”initial value of s.data  = “,s.data);
s.data = 25;
$display(”modified value of s.data = “,s.data);
$display(”value of t.data          = “,t.data);
end
endmodule

Result:
initial value of s->data  = 14
modified value of s->data = 25
value of t->data          = 25
Download here. singleton-design-pattern

C++ Singleton Example

Download here.  singleton-design-pattern

Purpose of a singleton:
To have a class which has only one instance(object)
All the objects of this class refer to same global object
that is created only once
This design pattern provides a mechanism for providing
namespaces to global variables

C++ example for singleton design pattern

// Filename  : singleton.cpp
// Author    : A.G.Raja
// License   : GPL
// Website   : http://agraja.wordpress.com

#include <iostream>

using namespace std;

class Singleton {
// constructor that is called only once
Singleton();
// object that is created only once
static Singleton *single;
public:
// method to get object
Singleton* get_instance();
// data to check the functionality
int data;
};

Singleton* Singleton::single = NULL;

Singleton* Singleton::get_instance() {
// call the constructor for the first time
// if the object has been created already
// return reference to the object already created
if(single==NULL) single = new Singleton();
return single;
}

Singleton::Singleton() {
data = 14;
}

int main() {
Singleton *s, *t ;
s = s->get_instance();
cout<<”initial value of s->data  = “<<s->data<<endl;
s->data = 25;
cout<<”modified value of s->data = “<<s->data<<endl;
t = t->get_instance();
cout<<”value of t->data          = “<<t->data<<endl;
}
// end of file singleton.cpp

Result:
initial value of s->data  = 14
modified value of s->data = 25
value of t->data          = 25

Download here.  singleton-design-pattern

System Verilog Virtual Interface

Download here. system_verilog_virtual_interface

// Filename    : virtual_interface.sv
// Author      : A.G.Raja
// License     : GPL
// Website     : http://agraja.wordpress.com

interface bus(input wire clk);
int address;
int data;

modport virtual_interface(input clk);
endinterface

module virtual_interface;
bit clk;
bus BUS(clk);
class monitor;
virtual bus VBUS;
task disp;
$display(VBUS.address);
$display(VBUS.data);
endtask
endclass
monitor m;

initial begin
m = new;
m.VBUS = BUS;
BUS.address = 100;
BUS.data    = 1234;
m.disp;
end
endmodule

// Running simulation in ncverilog
// ncverilog +sv virtual_interface.sv

// Running simulation in modelsim/questasim
// vlib work
// vlog -sv virtual_interface.sv
// vsim -c virtual_interface
// run

Download here. system_verilog_virtual_interface